Application Notes
1. Spectre PSPICE Netlist Support
Spectre technologyenables the user to include PCB components in PSPICE format into a Spectre integrated circuit simulation. The solution is based on the approach of using a regular Spectre simulation including the Spectre simulator control statements, but additionally allowing inclusion of user-defined sub-circuits in PSPICE format.
2. Setting Up Liberate MX for Various Usage Models
This application note is intended to assist you in understanding the purpose and method of Liberate MX and to guide you to choose the usage model that best suits the design that you are characterizing.
3. Liberate MX: Debugging Netlist Issues
When setting up an instance that is to be characterized using Liberate MX, the user needs to provide certain circuit information such as rails and bitcell. If the user does not provide sufficient information about this, the characterization does not run appropriately. In this application note, we will discuss the settings required to characterize an instance and how to determine if the required information is missing.
4. Characterizing Minimum Period and Minimum Pulse Width Using Liberate MX
The characterization of minimum period and minimum pulse width arcs are amongst the most complicated arcs in memory characterization. Each is made up of multiple components that must all be characterized with the maximum value being stored in the library file.
5. Using and Debugging the Liberate MX Validation Flow
The Liberate MX validation flow enables the user to test the numbers in a library file by running a simulation with minimum values for the stimulated arcs. This is commonly called an 'at speed' test. This test allows the user to verify that the memory is functional with the timing numbers in the library file.
Rapid Adoption Kits
6. Basic VCP/VSR Standard Cell Flow
Virtuoso Layout Suite XL and GXL products offer many assisted and automatic capabilities. With the continuous need for higher productivity, and more designs in the custom space, it makes sense to move to a slightly higher level of abstraction, which is referred to as a connectivity-driven design flow. Virtuoso Layout Suite XL is an answer. You can generate the layout based on schematic connectivity and then invoke Virtuoso Custom Placer (VCP) to do the standard cell placement. After placement, the design is ready to be routed.
Videos
7. Virtuoso Layout Suite: Improve Hierarchical Design Editing Performance Using Area Display Feature
9. Running AMS Simulation in ADE L Using AMS UNL
10. New Training Bytes Videos for Courses:
- Using Virtuoso Constraints Effectively
- Virtuoso Connectivity-Driven Layout Transition
Solutions
11. How bring the CIW window on top
I am using Virtuoso suite of tools for my design work. I have many design windows open, some may be iconified, some may be buried under other windows. My CIW window gets buried/hidden among these lots of windows. Is there a way to setup a keyboard shortcut so that I can bring the CIW window on the top/front/active whenever I need it?
12. How to redistribute Monte Carlo jobs in ADE XL to better utilize faster machines?
I would like to have the Monte Carlo jobs redistribute during the run. If the MC points assigned to Job on one of the machines in my queue finishes early, then the Job should not remain idle but it should take the MC points from other Job running on different machine.
In IC6.1.6.500.11 and later there is a change of behavior in OSS around how it handles two different place masters that point to same switch master.
14. How to see the amount of disk space used by a History item in ADE XL
You have many History items. You want to see how much disk space is being used by a History item. Is there a way to do this from ADE XL?
Dummies added to the layout can be added as individual devices, automated within a modgen or as a mosaic. We can back-annotate the dummies to the schematic for LVS and VXL binding. With a big device array we can can also have a large number of layout dummies (on the periphery). Back-annotation typically creates an individual schematic device for each. This can result in a large number of schematic dummies which dominate the actual schematic. Commonly such dummies are all of the same dimensions or parameters and connectivity. As such we could consolidate the dummy devices in the schematic. This is probably best handled by creating an iterated instance. However, presently it is not supported. Can we create modgen dummies as iterated instance in schematic?
16. How to exclude power pins when netlisting Verilog using NC-Verilog?
I am generating verilog netlist for my schematic design using NC-Verilog for schematic environment. I have power pins on my cellview which I don't want netlisted. How can I generate verilog netlist exlcuding the power pins?
17. How to create a ruler button on Create toolbar of Virtuoso Layout Editor
I am using Virtuoso Layout Editor to create and edit layout design. I know that I can invoke the Ruler from menu Tools -> Create Ruler or using bindkey k. However, is there is a way to add a ruler button on the Create toolbar of Virtuoso Layout Editor. The same toolbar which has Create Instance etc.
18. SKILL to convert all the top level shapes and vias in a layout to blockage
I have a partially routed layout design. I want to have routing layer blockage or obstruction created on all the top level shapes and vias. In general I want to delete the original shape and just keep the blockages or obstructions because I will keep it as a physical view which can be loaded in a layout later on. However, in some cases I may need the original shapes and vias as well.
19. SKILL script to print a list of unique cells used in a schematic or layout design hierarchy
I use Virtuoso Layout Editor and Virtuoso Schematic Editor to edit my layout and schematic designs. I know that Edit -> Hierarchy -> Print Tree functionality of Virtuoso gives a hierarchical tree of schematic and layout both indicating what all masters have been used at different level of cellview hierarchy. The tree typically provides the cellview masters which are unique only for one level of design. In other words, if a nmos1v is used at different levels of hierarchy then it gets listed at all levels of hierarchy and is correct. I want a list of unique masters for entire hierarchy rather than one level of design.
Stacy Whiteman