I won't even attempt to number the items this time, and I'll have to skip the individual bits of troubleshooting information (note to self: don't wait three months between blog posts). There has been a huge amount of content posted in the last three months of 2015. A great deal of it covers the new features in the Virtuoso IC6.1.7 release, which came out at the end of November. Be sure to check out all the new goodies.
Application Notes
Links to What's New documents, videos, and launch pages for the Virtuoso IC6.1.7 release. For a little light reading, the What's New presentation is over 500 pages. We've been busy!
Using calcVal or OCEAN PreRun for Calibration ADE XL
An introduction to using CalcVal or OCEAN prerun for Calibration in ADE XL.
Electromigration Analysis in ADE L and EAD
How to use simulation results from Virtuoso Analog Design Environment L as input to electromigration checks in the electrically aware design flow.
Three presentations by Cadence experts from the International Microwave Symposium 2015:
- Multiple Dividers in Harmonic Balance
- Faster Triple-Beat Analysis for Receiver Design
- Advanced S-Parameter Modeling with Broadband SPICE Technology
VDR DRC Flow Based on Simulation-Net-Voltage Annotation File
This application note covers the PVS VDR solution, which relies on voltage labels in the layout to verify VDR spacing rules. The results of VDR spacing rules are reported as DRC violations, showing the layout shapes violating the checks.
IC6.1.7 Performance Improvement-Stream Translator
To speed up the performance, you can now avoid writing the OA database on disk and instead directly edit it in the virtual memory.
IC6.1.7 Performance Improvement-True Rendering
Improve performance when displaying a design in very high resolution.
Virtuoso IC6.1.7 Usability Improvement SPD (Symbolic Placement of Devices)
This document explains the usability improvement provided with the SPD (Symbolic Placement of Devices) feature.
IC6.1.7 Performance Improvement - Dynamic Measurement
Provide a new tool to dynamically display a measurement.
Smart Display Usability and Productivity Improvement
The goal of the tool is to make the layout easier to understand by displaying key information only.
IC6.1.7 Performance Improvement - Fast Drag
Improve performance when dragging geometries in VLS–L. It applies to commands such as fit all, zoom, move, pan.
Virtuoso IC6.1.7 Usability Improvement -True Color Probe
Probing now supports True Color.
Dynamic Selection Assistant (DSA) -Usability Improvement
Provide dynamic highlight and view layer stack (as if it is a flat design) in VLS-L.
Rapid Adoption Kits
Voltage Dependent Spacing Rules (VDR) Flow
This RAK covers the flows available in the Cadence custom IC design tools to create layouts that abide by voltage-dependent spacing rules (VDR).
Constraint-Driven Custom Design
The constraint-driven flow enables you to capture and transfer design requirements formally through the Constraint Management System, and then use automatic and interactive tools to enforce the requirements in the layout to ensure convergence on design goals.
This RAK/workshop database describes the usage of the Spectre APS/XPS static and dynamic design checks available in MMSIM. These checks may be used to identify typical design problems including high impedance nodes, DC leakage paths, extreme rise and fall times, excessive device currents, setup and hold timing errors, voltage domain issues or connectivity problems. While the static checks are basic topology checks, the dynamic checks are performed during a Spectre APS/XPS transient simulation.
IC 6.1.7 Pin To Trunk New Features
The objective of pin-to-trunk routing is to increase layout productivity through improved routing functionality. Pin-to-trunk routing enables users to quickly connect device or block pins in a structured topology.
Liberate MX for Characterizing Embedded SRAM Instances
Embedded Static Random Access Memory (SRAM) instances require timing, power, pin capacitance, and noise information captured in liberty (.lib) files to be used in full-chip static timing analysis (STA) flows. As embedded SRAM takes up increasingly larger chip area, it becomes important to generate the .lib files accurately and efficiently. The size and complexity of these memory instances can make manual approaches difficult and error prone. Liberate MX is architected to characterize embedded memories such as SRAM, ROM, CAM and so on for timing, power, and noise.
Check & Assertions in Virtuoso ADE XL
This flow includes features to enable the user to create circuit checks (Spectre static and dynamic statements) and device checks (Spectre assert statements) using the Checks/Asserts assistant, use built-in filters and create custom filters to aid in finding and debugging different types of check and assert violations, use the Checks/Asserts violations viewer to analyze violations, interactively cross-probe critical instances and nets in the schematic, and highlight problem areas on the waveform viewer, add violation waivers and overlay a set of waivers across subsequent simulations.
Post-layout Extraction Flow: Using BlackBox-PVS LVS and QRC Extraction Methodology
The scope of this document is to demonstrate the PVS LVS-blackbox and Quantus QRC parasitic extraction flow methodology. The methodology can be used to selectively check the impact of parasitics on a block-by-block basis by selecting the appropriate view of blocks (top level as well as sub-blocks that have been chosen as black-box during LVS) in the Hierarchy Editor, and finally, by running netlisting and simulation through ADE, and watching and comparing Simulation waveforms, etc.
Virtuoso Wire Editor 6.1.6 Behaviour and Commands
This workshop will cover controls, settings, and use models for the Virtuoso interactive Wire Editor.
On occasions, the engineer working on layout needs to add or remove a level of physical hierarchy to complete the layout. Examples of this are creating a half cell or a unit cell to reuse existing layout to accelerate the layout process. In earlier releases these steps would break the XL compliance of the layout meaning rework in VLS XL/GXL. This RAK explains the improved functionality in this area and shows how it can be used to maintain the correspondence to the schematic.
Videos
Demo for command Align and Distribute in VSE in IC 617.
This video shows the two modes, Pre-Select and Post-Select mode, to put the off-grid objects in the schematic on grid.
After viewing the video, you will learn the technique to simplify the addition and visualization of Ignore property on instances.
You can specify a search region. The search region can be the Entire CellView, the current Viewing Area, and user-drawn rectangle region or a polygon region. Smaller search region would reduce the search time and the number of search results.
How to Use Copy Connectivity Option in Copy Command
How to Use Smart Snapping of Ruler in Quick Align Command
True Rendering - Performance Improvement
This video demonstrates the performance improvement provided with the True Rendering feature.
The new Net Name Display Option in Virtuoso IC6.1.7 allows users to view the net name inside a shape. The color of the net name display label is user selectable. The label can be placed above the shape to improve visibility.
SPD - Symbolic Placement of Devices
This video explains the concept of Symbolic row-based Placement of Devices (SPD), shows how to use SPD and how layout productivity can be improved.
True Color Probe - Usability Improvement
This video demonstrates the usability improvement provided with the True Color Probe feature.
Dynamic Selection Assistant (DSA) - Usability Improvement
Dynamic Measurement Usability Improvement
Drag - Performance Improvement
This video demonstrates the performance improvement provided with the Fast Drag feature.
This video is based on Virtuoso IPVS RAK database. Virtuoso IPVS is a mechanism where the PVS verification tool is tightly integrated with the Virtuoso platform. Virtuoso IPVS uses foundry supplied sign off rules to verify your design. When design complexity grows, finding errors as you design gives you the opportunity to correct the errors or redesign the layout early in the design phase. Also, using the signoff rules from the foundry while designing exposes violations caused by complex rules early. These violations might be difficult to correct later in the design cycle. Overall, verifying your layout as you go along using Virtuoso IPVS can reduce your project completion time when compared to verifying your layout after you complete the design. This video covers the following topics: The Virtuoso IPVS Toolbar; Verify Design mode; Virtuoso IPVS Predefined Filters; Using the Post Edit Mode of Virtuoso IPVS.
Starting Virtuoso IC 6.1.7, the text associated with Pins can be created as “Labels”, the text associated with Labels in ‘Auto Label mode’ can be created as “Labels."
Partial Selection of Fluid Guard Ring (FGR) in Pre-select Mode
In IC617, a new partial selection of Fluid Guard Ring (FGR) option allows users to partially select Fluid Guard Ring in pre-select mode. After viewing this video we will understand: Variables supportFluidInstance and selectPartialFluidInstance need to be set for partial selection of Fluid Guard Ring in pre-select mode. User can select an edge or corner of the Fluid Guard Ring before a command (e.g. stretch) is invoked.
Describes the latest changes in the Navigator assistant.
After viewing this video, you will be able to create boundary cells that surround standard cells.
IC617 Pin To Trunk (P2T) Introduction
This What's New video will take you through the available options for doing pin-to-trunk routing in IC617.
This video, "P2T Usage" is the second of a two video set to describe the new IC.6.1.7 pin-to-trunk interactive and automatic routing features. The first video in the set is called "P2T Introduction."
How to set up checks and assertions in Virtuoso ADE XL
Learn how to set up the circuit checks (like static and dynamic) and device checks (with Spectre assert statements) in Virtuoso ADE XL.
How to filter and view the violations of checks and assertions in Virtuoso ADE XL
Learn how to filter and view the the circuit checks (like static and dynamic) and device checks (with Spectre assert statements) violations in Virtuoso ADE XL.
New Training Bytes videos from the following training courses:
- Virtuoso Layout Pro
- Virtuoso Spectre Pro
- SKILL Language Programming
Stacy Whiteman