Device variation has been a long-standing problem in custom design.  Over the years, our customers have made many attempts to model the behavior though parameterization, simulation model extensions, sub-circuits, and by just "guessing" as to what might happen. As the mathematical complexity of each node increases, so does the difficulty of making sure all the design possibilities are covered during the initial design phases. That's where the Virtuoso Analog Design Environment GXL can be useful. 

Created to use all of the tests and measurements developed inside Virtuoso Analog Design Environment XL, the GXL tool can help you during four distinct design phases: 

1.    Pre-design by helping the engineer retarget existing IP to new processes

2.    In-design by providing a host of sophisticated tools for developing worst case corners, yield improvement mini-flows using matching, tuning, and optimization, and high-yield analysis for discovering circuit behavior at 6-sigma.

3.    During physical implementation by allowing the designer to take "snapshots" of the partial layout to see how parasitics from routing or placement could be skewing the desired results before the design is completed and locked down.

4.    Post-extraction, verifying the design is still meeting specification even after the full hierarchical physical implementation is completed  

With Cadence's unique token licensing within the Virtuoso Analog Design Environment GXL platform, licenses never sit idle since the tokens are flexible enough to cover all of the technology or be used to run ADE XL/L cockpits when not needed for variation design. That makes the adoption of Virtuoso Analog Design GXL easy technically and easy on the budget. Over the next seven weeks, our technical experts here at Cadence will be showcasing six major capabilities contained within the tool:

a.    Creating and using worst case corners

b.    Fast yield analysis and statistical corners

c.    Mismatch variance contribution and yield contribution

d.    Design migration and retargeting

e.    Circuit tuning and optimization

f.    High yield analysis and optimization 

Check into the Custom IC Community regularly to see the latest information. And please speak with your Cadence representative to learn more about the Cadence offerings or to see a demonstration of how the technology can help you.  If you haven't looked at Virtuoso Analog Design Environment GXL in awhile, then you don't know what you are missing!  Let us show you today.

Steve Lewis

Fast/slow, high/low, pre/post.  If I have to spend the time to run all the possible combinations, I won't have much time left to tune my design. But how do I really know which combinations are going to be the worst case for each of my specifications? 

This is exactly the problem addressed with the Worst-Case Corners (WCC) run mode in the Virtuoso Analog Design Environment GXL (ADE GXL). 

The approach is straightforward, the setup is simple, and the results are powerful.

The Approach-Framing the Problem

Worst-Case Corners follows a basic Design of Experiments (DoE) methodology.  That is, given a set of input variables (your corner parameters and their values), and a set of measured output responses (your testbench measurements), a number of trial sets of input values are intelligently chosen and simulated. The results are observed and analyzed and then one corner is created for each specification containing the combination of variable values which has been determined to give the "worst" result.  (Two worst corners are created for range and tolerance type specs.)

In general, process corners are given special treatment during trial creation, since there is inherently no natural sequence to the list of model sections. Thus, all process corners are considered in simulation.

The Setup-What Goes In?

WCC works with your existing ADE XL testbenches, measurements and specifications.  You can use the corners you already have defined in ADE XL as input for the WCC setup, or you can specify any combination of variable values to be considered.

Several methods are provided to trial experiment selection and corner creation. You choose the method based on the linearity of your circuit response and inter-relationships of your input variables.  Standard DoE and response surface methods (RSM), such as one-factor-at-a-time (OFAT), Central Composite and Factorial, are supported to give a full spectrum of analysis capabilities and performance. 

The number of simulations required to determine the worst-case corners depends on the number of variables and the number of values for each variable.  Typically, on the order of 30-50 simulations are run for most common corner setups.

The Results-What Comes Out?

At the conclusion of a run, worst-case corners are created for each specification in your ADE XL setup.  Depending on the method used, the created corners will be simulated and validated against the models used to identify the worst-case variable values.

In addition, the results of the simulations are analyzed for sensitivity and displayed in an interactive table, allowing you to further examine the characteristics of your circuit's responses to each variable as well as how each factor contributes to the overall variation in circuit performance.

Now that you have created the worst-case corners for your design, you are well-positioned to efficiently optimize your design, either manually using ADE XL, or by taking advantage of advanced ADE GXL analyses such as Sensitivity Analysis and Circuit Optimization.

Time just got away from me last month, so here's two months worth of new content for your browsing enjoyment...

Videos

1. Integration Constraints Capability used in Mixed Signal Design Implementation

Explains and demonstrates the integration constraints capability of the Cadence Mixed-Signal Solution.

2. Virtuoso Floorplanning Design Flow Demo

Demonstrates the Virtuoso Floorplanner Flow: soft and hard blocks, defining cell type attributes, configure physical hierarchy (CPH) – soft block parameters, generate physical hierarchy, block placer, snap pins, editing soft blocks, and pin optimization.

Rapid Adoption Kits

3. Electrically Aware Design (EAD) Workshop

Covers the main functionality of EAD, which is a flow that allows extraction of layout parasitics at any point in the design cycle.  You can resimulate with parasitic effects using layouts that are incomplete.  This flow also supports electromigration analysis based on Spectre simulation results. Includes detailed tutorial and database.

4. IC 6.1.6 Pin To Trunk Device-Level Routing

Steps through the Pin to Trunk Device-Level Routing Flow in Virtuoso in IC6.1.6 ISR4.  This flow enables users to quickly connect device pins in a structured topology.  Includes detailed tutorial and database.

5. IC 6.1.6 Pin To Trunk Block-Level Routing

Steps through the Pin to Trunk Block-Level Routing Flow in Virtuoso in IC6.1.6 ISR4.  This flow enables users to quickly connect block pins in a structured topology.  Includes detailed tutorial and database.

Solutions

6. Fluid Guard Ring Frequently Asked Questions

This is a compilation of the most popular solutions related to fluid guard rings.

7. AMS Designer in ADE FAQ

Answers to customer's most frequently asked questions about the interface to the Virtuoso AMS Designer Simulator in ADE.

8. BindKey Quick Reference in Virtuoso Schematic Editor

A handy chart of all the default bindkeys for the Virtuoso Schematic Editor--single key, Ctrl, Shift and Ctrl-Shift versions, plus function keys--in a concise keyboard layout.

9. bindKey Quick Reference Guide for Virtuoso Layout Editor

A handy chart of all the default bindkeys for the Virtuoso Layout Editor--single key, Ctrl, Shift and Ctrl-Shift versions, plus function keys--in a concise keyboard layout.

10. How to print Monte Carlo statistical parameters greater than 1900 in ADE XL?

A little piece of SKILL code to dump all the values of statistical parameters for each point in a Monte Carlo run to a CSV file.

11. PVS Quick Reference and Frequently Asked Questions

Concise and handy quick reference document on how to use the PVS tools to work with designs, including how to verify a layout against physical design rules and schematics.

Blog Articles

12. Have You Tried the New Transmission Line Library (rfTlineLib)?

An overview of the new RF transmission line library in IC6.1.6 ISR1, which contains wideband-accurate transmission line models in multi-conductor microstrip and stripline configurations.  They are integrated in Virtuoso ADE and accessible from stand-alone Spectre netlists.

13. What Your Circuit Doesn't Know, Can Kill It!

Introduces an upcoming series of articles covering the advanced capabilities of Virtuoso Analog Design Environment GXL to handle variation-aware design issues, such as finding worst-case PVT corners, performing efficient statistical and mismatch analysis, circuit optimization and design migration.

14. What's the Worst That Could Happen?: Worst Case Corners in ADE GXL

This is the first in the above-mentioned series of articles and covers an ADE GXL analysis which enables you to quickly identify the worst case PVT corners for each of your design specifications so you can save time during design iterations and ensure your design is robust.

Stacy Whiteman

The Virtuoso Analog Design Environment XL Monte Carlo sampling methods are Random, Latin Hypercube, and Low Discrepancy Sequence.  More accurately, Spectre provides the engine and ADE XL interfaces with the simulator to complete the Monte Carlo analysis task.  Random is the standard random sampling method.  Latin Hypercube (LHS) is an enhanced method that converges faster.  Low Discrepancy Sequence (LDS) is the most recently developed method.  Experimental results that compare the three methods are shown in the figure below.

Phase Margin of an op amp is measured and the mean error is compared to the golden result of 100K Monte Carlo samples.  Each data point represents the result of 20 independent trials.  The mean error is:

This is only one example but, in general, LHS and LDS results are found to be comparable.  An advantage of LDS over LHS is that it is compatible with the ADE XL feature to automatically stop the Monte Carlo run given a yield estimate target.  Provide a yield target and Monte Carlo will stop performing simulations when the design is either found to exceed the target or found to be low yield.  This saves time by not running any more simulations than necessary based on the specified significance level.  If needed you can loosen the significance level to get results faster or increase the level depending on your requirements.

Once the Monte Carlo results are available, statistical corners can be created.  In ADE XL you can create a statistical corner from any of the simulated samples.  There are several options to create the corner, including selecting a point on the histogram, creating a corner out of the worst sample, or by percentile.

ADE XL saves only the relevant information such as seed, sequence number, sampling method, etc. with the corner. Spectre can then recreate the statistical parameter values for the corner from this information. This type of corner is efficient and does not require that all the statistical parameter data for each sample is saved in Monte Carlo.  The downside is that some changes to the design topology such as the addition of a new instance to the schematic can invalidate the corner.  The simulator can no longer recreate the same set of statistical parameter values when simulating the statistical corner.  Two types of statistical corners are possible in ADE XL with version IC6.1.6 ISR6; a corner with the sequence info saved, or a corner that contains all of the statistical parameter values.  The values-based corner is more robust in the face of these minor design changes. The new instance added to the design does not invalidate the existing statistical corner of this type. The user can choose which corner type better suits their needs.

All of the above methods define the corner by one of the simulated Monte Carlo samples.  To create a 3 sigma statistical corner you must have simulated a large number of samples.  A new ADE GXL feature to be released with IC6.1.6 ISR6 addresses this problem.  The goal is to create a k sigma statistical corner quickly (by default 3 sigma - you can specify the yield-in-sigma target) without the need to run thousands of simulations.  The fast 3 sigma corner flow is to:

• Run Monte Carlo (only a few hundred samples compared with the traditional approach requiring 1000+ samples)
• Create the fast 3 sigma statistical corner

A minimum of 1 and a maximum of 11 extra simulations per corner are needed for this step.

The fast 3 sigma corner algorithm estimates the probability density function (PDF) of the performance distribution maintaining accuracy for non-normal distributions.  The specification target value is computed from the PDF estimate.

A statistical corner is then created that matches the target spec value.  There can be multiple corners that meet this criteria.  This method finds the most representative corner by minimizing the distance to the nominal point.  This representative corner has a greater probability to occur.  Now the statistical corner can be used for further analysis of the design.  Look for this feature in ADE GXL in the next IC6.1.6 release.

Lorenz Neureuter

Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes.  However, redesign of circuitry is time-consuming, so it is common to migrate existing designs from previous projects, often from one process node to another.  Additionally, migration is also required for:

• Second sourcing on a similar process from a different foundry
• Reusing IP in next-generation process nodes
• Providing variant IPs with different requirements

Migration of analog circuits is often a cumbersome and designer-intensive process.  When migrating a block that has already been designed, verified, and tested to a new process, it is often desirable to maintain the same architecture and in many cases the same or similar circuit performance of the original source design. The following provides an overview of a methodology for performing such a process migration for schematics and testbenches.

Cadence's Virtuoso Design Migration flow consists of:

• Validation of source circuit performance
• Schematic migration
• Assessment of target circuit performance
• Optimization of target circuit to achieve desired performance

The Virtuoso Design Migration flow is a methodology-driven activity, assisted by automation.There are three major phases - PDK and design assessment, design environment preparation, and design migration and verification.The software used to assist the user is contained within Cadence Virtuoso Analog Design Environment GXL as a part of the optimization tool suite.

PDK and Design Assessment

Before relying on assisted automation, a successful migration requires a careful assessment of both the source and target Process Design Kits (PDKs).  This assessment will help to determine the level of automation that can be applied to the migration or re-design required by determining device correspondence between the source PDK and the target PDK. Once a device correspondence is established, there are several challenges that will determine how well the source design can be migrated. Some of these challenges include symbol compatibility, mapping of passive devices (which can result in fairly large changes in layout area), and design type as this will dictate the level of automation which can be applied during migration. For example, migration of analog blocks function with rail-to-rail voltage margin can be automated significantly more than RF blocks or blocks which are affected by low voltage differences.

Design Migration and Verification

The design migration process starts by replacing the source PDK devices with the mapped devices from the target PDK in each block to be migrated.  This is typically a fairly automated process. The target schematic is then substituted into the testbench schematic. Following migration, the verification plan which was run on the source design is rerun on the target design. The results are compared against the specifications and against the performance of the source design.  If necessary, the block can be optimized to achieve compliance with the specification.

The diagram below outlines a typical front-end migration flow.

A workshop is available which demonstrates this methodology and provides additional details.  You can contact your local Applications Engineer to access this workshop or for additional assistance.

Tom Volden

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. You can also compare the relative importance of the contributing instances.  The analysis results can aid in making design changes to reduce the variation.  Mismatch Contribution is a variance-based global sensitivity analysis ^[1].

Mismatch Contribution is launched from Monte Carlo results.

 Here is a flat view of the outputs, and mismatch parameters are displayed and sorted by the swing specification.

Each device instance may be modeled with multiple statistical mismatch parameters.  The parameter names themselves are not always of interest.  In some cases the PDK models are derived from principal components.  Mismatch Contribution provides a hierarchical view where the total contribution of all of the device parameters is displayed for each instance.  The hierarchical view reports the contributions by instance for quick identification of important instances.

Cross probing to the schematic is provided.  The schematic is opened to the same level of hierarchy, and the selected instances are highlighted.  Navigate the table as you would a schematic.  Descend into a row (instance) of the table until reaching the leaf level.  The leaf level again displays the individual mismatch parameters of the instance.

By contrast, a top-level view with four blocks shows the block contributing the most variation of the specification.  Descend to find the lower-level contributors.

When global process variation is applied during the Monte Carlo analysis, the contributions from the process parameters are included in the contribution analysis.

Mismatch Contribution is not limited to linear effects.  When a linear model of the data is insufficient, a quadratic model is automatically applied.  The R^2 value in the header of the table for each specification is the proportion of variance explained by the model.  This is the goodness of fit of the model.  Sparse regression techniques allow for computation of the contributions even when the number of parameters is very large compared to the number of Monte Carlo samples simulated ^[2].

Mismatch Contribution is available now in Virtuoso ADE GXL, first released in IC6.1.6 ISR3.

[1] http://en.wikipedia.org/wiki/Variance-based_sensitivity_analysis 
[2] J. Tropp and A. Gilbert, "Signal recovery from random measurements via orthogonal matching pursuit," IEEE Trans. Information Theory, vol. 53, no. 12, pp. 4655--4666, 2007.

Lorenz Neureuter

Development Model for ADE and ViVA

Virtuoso Analog Design Environment (ADE) and ViVA follow a development model that allows new content to be added in every third ISR.  These content ISRs receive additional usability testing, product validation, and demonstrations and beta testing with customers. This development model gives R&D long enough development cycles to add meaningful content while ensuring that quality and stability of the main ISR stream is not compromised.

While this development model provides an excellent method to deploy new features and functionality in a frequent but controlled manner, it also presents challenges in making customers aware of the new capabilities.  This blog post outlines some of the new features that first appeared in ISR 3, which was released in November (hence the "-ish" in the blog title).  The next content release, ISR 6, will be available at the end of April so look for a fresh post with additional new items soon.

So let's get too it!  What's New(-ish) in ADE XL in 616 ISR 3?

• Performance and stability improvements when working with a large number of corners
• Better handling of disk full and other conditions which previously resulted in crashes
• Usability improvements in Annotation Balloons based on user feedback
• Ability to add user defined columns in ADE XL outputs setup and results table
• Allowing individual ICRP processes to be stopped and resubmitted
• Improved error debugging and access to job log
• Setting default results view for single run, sweeps and corners
• Measurements tied more tightly to analyses
• Improved use model for pre-run scripts
• More efficient use of disk space when a netlist is re-used for all points
• Low Discrepancy Sequence (LDS) sampling method support for Monte Carlo
• Ability to launch Debug Environment for Monte Carlo points
• Sample points displayed on histograms with cross selection to ADE XL results table

What new feature are you most excited to see?  Are there other features that you would like to have to make your job easier?  Do you have questions about ADE XL or other Virtuoso products?  Leave a comment  below and I will try to address them in future blog posts.  Also watch this space for details about new features in ISR 6 when it is released at the end of the month.

Tom Volden

Highlights for this month include lots of useful Physical Verification System (PVS) appnotes and several blog articles on advanced analyses and flows in Analog Design Environment (ADE) GXL.

Application Notes

1. Physical Verification Checks and Generic Tips

Concise overview explaining the basics of the various DRC and LVS checks in rules files.

2. Recommendations and Tips for the PVS DRC Flow

Includes sections on preparation of runsets, running DRC, preparation of design blocks and DRC/LVS check of top-level GDS.

3. Recommendations and Tips for the PVS LVS Flow

Design and runset preparation, links to helpful solutions and sources of common errors.

4. Recommendations and Tips for the PVS Metal Fill Flow

Preparation of runsets, working with different fill scenarios and how to correct errors.

Rapid Adoption Kits

5. Making a layout XL-compliant using Update Binding (XLME)

Uses a sample design scenario to explain how the Update Binding command can be used to increase the VLS XL-compliance of a design using the physical connectivity in the layout and the output from a PVS LVS run. 

6. PSPICE netlist support in ADE

Describes the integration support in Analog Design Environment (ADE) to include a netlist in PSPICE format.

Solutions

7. Why isn't there an hbxf in the Choosing Analyses form?

You have recently started using the GUI for hb analysis and the associated small signal analyses. You noticed that there is a periodic xf (pxf) small signal analysis for pss. Why isn't there a similar analysis (hbxf) for hb?  Click on the link to find out.

8. Is PSF-XL supported for AMS simulation?

(Spoiler Alert) Why yes.  Yes it is.  This solution will tell you how to use this faster analog waveform format. 

9. Why do we have mulitple MMSIM13.1 hotfixes on downloads?

Several MMSIM 13.1 hotfix versions are being maintained on downloads to accommodate specific foundry/PDK rollouts.  Click the link for more information.

10. How to create a form showing a thumbnail image of the cellView

Wow, this could be fun.  A while ago, I wrote an article about how to create thumbnail images.  Now you can find out how to include those images in your own forms.

11. Does bindkey work with forms?

This solution provides an example of how to create a form in which you can register your own set of bindkeys.

12. How to create a custom RAP generator that creates additional constraints?

I would like to modify the existing CurrentMirror generator code to create additional constraints, for example, orientation and matched parameter constraints in addition to the modgen constraint. Here is that sample code.

Blogs

13. Fast Yield and Statistical Corners

Describes the different sampling methods available in ADE XL Monte Carlo analysis, the advantages of using auto-stop if you don't know how many samples are needed, and the types of statistical corners that can be created from the Monte Carlo results to help the designer improve circuit yield.

14. Efficient Design Migration Using Virtuoso Analog Design Environment GXL

The article provides an overview of a methodology for performing process migration for schematics and testbenches, including PDK and design assessment, design migration and final verification.

15. Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. The article describes the concepts behind this analysis how to use it.

Stacy Whiteman

Anyone who has ever played a musical instrument knows how hard it can be to keep the instrument in tune when subjected to variations in weather conditions. Heck, in 2009, Yo-Yo Ma and friends (sorry, he gets top billing because I used to play the cello) pantomimed their performance at the Presidential Inauguration because their instruments wouldn't function properly in the frigid temperatures. Guess they didn't want to risk sounding like my seventh-grade orchestra in front of that large an audience. 

Well, we've been talking a lot in this blog recently about the problems caused by the effects of variation on circuit design, and the risks of being "out of tune" can be just as great when it means your chip is late or doesn't work properly.

• How to sort through hundreds of combinations of PVT corners to find the ones that really matter
• How to efficiently analyze and design across statistical process and mismatch variation
• How to smoothly migrate a design from one process node to another while maintaining circuit performance
• How to quickly identify which parts of the circuit to tweak so statistical mismatch effects won't throw your design out of spec

Today we're going to talk about some of the features available in the Virtuoso Analog Design Environment GXL (ADE GXL) to help you tune your circuit to overcome the effects of variation on circuit performance. Let's start by putting things in the context of an overall flow that looks like this:

Setup and Corner Creation

The basic idea here is that you start with a test setup in ADE XL, which can consist of multiple testbenches, each with a set of output measurements and design specifications. Then you add the relevant corners, which will cover the limits of the design performance across which you need to optimize. These can be your standard PVT corners, they can be a critical subset of corners generated using the ADE GXL Worst Case Corners analysis, or they can be statistical corners generated from a Monte Carlo analysis to capture 3-sigma or other outlying statistical behavior for each of your design specifications. 

Parameterization

One of the keys to getting the most out of the circuit-tuning capabilities in ADE XL and ADE GXL is device parameterization. I've written about this feature before, but to recap, the Variables and Parameters Assistant in ADE XL allows you to create parameters for any device properties and vary them at will without having to edit the schematic. You can also incorporate critical device matching and ratioing relationships. 

The "Create Parameter Range" option will automatically create a +/-% range on any parameters, which makes sensitivity analysis and optimization a snap.

Sensitivity Analysis

Sensitivity Analysis in ADE GXL allows you to get a good idea of the criticial devices in your circuit and their effects on design performance. With only a few targeted simulations, you can find out which devices in your circuit have the most impact on each of your design specifications, as well as how changing a device size whether changing a device size to improve one spec will adversely change the other specs.  Device parameterization makes it quick and easy to evaluate "what-if" scenarios until your desired performance is achieved.

Local and Global Optimization

The optimization algorithms in ADE GXL have been proven within our customer base for many years. The optimizer works across all the multiple testbenches, specifications, and corners you already have set up, including the worst-case PVT and statistical corners you have defined to capture the extreme boundaries of your circuit behavior. Device parameters are intelligently varied over the ranges you have defined until all design specifications have been met. Simulations are distributed using ADE XL's job distribution system to maximize the efficiency of the analysis.

ADE GXL provides four local optimization algorithms: BFGS (recommended for most common analog circuits), Conjugate Gradient, Brent-Powell, and Hooke-Jeeves. Use these when you have a reasonable degree of confidence in your initial circuit starting point values. If you aren't sure of your starting point, use Global Optimization, which will perform a much broader exploration of the design space to find viable circuit solutions.

Several additional optimization-based run modes are available, including Size Over Corners to efficiently optimize over a large number of corners and Improve Yield, which combines Monte Carlo analysis and automatic statistical corner creation with iterations of circuit optimization to center your design within statistical process and mismatch variation.

Verification

"The proof of the pudding", as they say, "is in the eating," so the final step in our big red PowerPoint SmartArt arrow above is to verify the results of the circuit tuning. This may involve running a final simulation across all PVT corners or a final Monte Carlo analysis to verify the optimized design can overcome the effects of all types of variation.

In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3.  Here are more new features that are now available in Virtuoso ADE XL in the recently released ISR6.

• Notes can be added to tests, variables, corners, parameters, and histories. This allows you to document information about important items in your setup or make notes about a particular history to document simulation conditions, results, or other key information.
• Comma separated value (CSV) files can now be used to import and export corners setup. This improves the use model for managing corner setups in external editors. Prior to this enhancement, import/export required the use of more complicated XML format from the Virtuoso ADE XL setup database (SDB).
• Ability to cancel selected tests and corner points. Previously, stopping a run canceled all running and pending simulations. The new feature allows you to selectively cancel individual simulation for a particular corner or test. Remaining tests and corners will continue to be run.
• Creation of K-sigma corners from limited Monte Carlo samples. The new algorithm estimates the Probability Density Function and computes the corner specification value based on that PDF. A statistical corner that matches the target specification value is then created. This is an improvement over previous methods for creating statistical corners with a particular standard deviation as they required a large number of Monte Carlo points to achieve accurate results.
• Ability to filter evaluation and simulations errors from yield estimate in Monte Carlo simulations
• Wild card selection is now supported in the Annotation Setup form
• Value-based statistical corner creation from Monte Carlo simulation is available. This allows the distribution point to be maintained with minor changes to the design such as addition of new device instances. Prior to this, any changes to the design which impacted connectivity would invalidate the statistical corner.

What new feature are you most excited to see?  Are there other features that you would like to have to make your job easier?  Do you have questions about Virtuoso ADE XL or other Virtuoso products?  Leave a comment  below and I will try to address them in future blog posts.

Tom Volden

One failed memory cell out of millions cells will cause the whole memory circuit to fail without ECC (error checking and correction) techniques. That is why memory designers have high parametric yield requirements for the SRAM core cell. It requires no fails in hundreds of millions or billions of brutal force Monte Carlo simulations if foundry statistical models are accurate up to the high sigma region.Memory circuit designers also have high yield requirements for other circuit block and memory partitions, such as sense amplifier sor critical-path partitions.

How to analyze high yield and debug, improve the design in Virtuoso ADE

Virtuoso Analog Design Environment GXL selects WCD (worst case distance) metric-based method as its high yield solution. To estimate high yield, ADE GXL will first find the WCD point in the statistical space.Once the WCD point is found, the yield can be calculated directly using the WCD.

The accuracy of WCD is impacted by nonlinearity of spec boundary in statistical spaces. However, that error is not significant in most high yield applications. The WCD point has the shortest distance from nominal point to fail region in statistical space. It is also the most probable point to fail in statistical space. During a continuously running Monte Carlo process, the first failing Monte Carlo point has a very high probability to be very close to the WCD point in statistical space.This makes the WCD point very attractive for creating a high-yield statistical corner because it captures the circuit condition with the highest probability to fail.This point becomes increasingly important if designers want to debug and improve the design. Based on the WCD point, Virtuoso ADE GXL provides the capability to create a high-sigma corner to improve the yield. 

The completed high yield solution in Virtuoso ADE GXL is a part of the TSMC AMS reference flow. It includes:

1.    High yield calculation

2.    Creation of high yield statistical corner

3.    Optimization of the design with high yield corner

4.    Verification of design using high yield calculation

What is coming next? New algorithms for high dimension!

Cadence R&D co-invented the next-generation high yield estimation algorithm with researchers from Carnegie Mellon University recently[1]. The scaled-sigma sampling algorithm works well with high-dimensional nonlinear problems, which exist in large circuit blocks. Please stay tuned!. The algorithm will be publicly available in the coming IC616ISR release.

[1] Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo and Ben Gu, "Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 478-485, 2013.

Plenty to keep you busy this month.  Lots of RAKs, videos, and new Quick Start Guides and FAQs.

Application Notes

1. Using Annotation Browser with Virtuoso IPVS

Learn how to invoke the Annotation Browser and have it always appear docked to a specific location of the layout window, how to customize the Annotation Browser, and how to automatically set the visibility of the error markers.

2. AMS Designer INCISIVE Command-line Flow Use Model (updated)

Provides an overview on how to run mixed-signal simulations from the command line using the irun command.

3. Spectre PSPICE Netlist Support

Provides a means for designers to analyze IC and PCB components together in the same simulation by including PCB components in PSPICE format into a Spectre integrated circuit simulation.

Rapid Adoption Kits

4. Analog Design Environment XL (ADE XL) Workshop (updated)

Virtuoso Analog Design Environment XL provides a multi-test simulation environment for thorough design validation, extensive design exploration, IP reuse, and early insight into manufacturing variability. This material has been designed to highlight many of the features as well as key functionality of ADE XL. Includes new features in ADE XL up through IC 6.1.6 ISR6.

5. Virtuoso Visualization and Analysis (ViVA) (updated)

The Virtuoso Visualization and Analysis tool is an analog/mixed-signal waveform viewer providing the means to thoroughly analyze the data generated by circuit simulation. Learn how to use it either as a standalone tool or as an integrated part of the Virtuoso Analog Design Environment (L and XL). Includes new features in ViVA up through IC 6.1.6 ISR6.

6. MODGEN

Module generators are designed to provide a way to generate multiple Pcell instances into a complex, highly matched, structured array. With the Modgen tool, you specify the devices to be arrayed, then specify an interdigitation pattern, and insert dummy devices, body contacts, and guard rings. Finally, you control the routing style and generate internal routing geometry.

7. Virtuoso IPVS

Virtuoso IPVS is a mechanism where the PVS verification tool is tightly integrated with the Virtuoso platform. This RAK includes an introduction to Virtuoso IPVS and covers how to get started, the different modes of Virtuoso IPVS, how DRC violations are created and displayed for each mode, and how to customizde the rules for your design.

8. Static and Dynamic Checks (updated)

This material describes the usage of the Spectre APS/XPS static and dynamic design checks available in MMSIM13.1.1. These checks may be used to identify typical design problems including high impedance nodes, DC leakage paths, extreme rise and fall times, excessive device currents, setup and hold timing errors, voltage domain issues or connectivity problems. While the static checks are basic topology checks, the dynamic checks are performed during a Spectre APS/XPS transient simulation.

9. Introduction to Device Safe Operating Area (SOA), Circuit Conditions, and Asserts Workshop

This material highlights some of the ways that the user can set up and check for circuit conditions, perform device checking, and handle operating regions checks.

10. Mismatch Contribution

Mismatch Contribution analysis is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify the identified devices in the design to make the design less sensitive to device mismatch variation.

Videos

11. Shortcuts to Improving Productivity Series

A three-video series describing shortcuts for improving productivity in Virtuoso Schematic Editor (VSE).  Includes Editing Canvas (tips for quicker schematic drawing and editing), Customization, and Setting Colors and Backgrounds.

12. IC6.1.6 Pin-to-Trunk Block-Level Routing Series

A three-video series describing pin-to-trunk block-level routing.  Includes Basics, Using Pin-to-Trunk Routing to Route Between Blocks, and Pin-to-Trunk Routing Using the Finish Trunks Command.

13. IC6.1.6 Pin-to-Trunk Device-Level Routing Series

A four-video series describing pin-to-trunk device-level routing.  Includes Basics, Pin-to-Trunk Routing with Wire Assistant Overrides, Pin-to-Trunk Routing with Routing Scope and Via Control, and Pin-to-Trunk Routing Using the Finish Trunk Command.

Blogs

14. What's New(-ish) in ADE XL in IC616 ISR3?

Discusses new features in ADE XL in IC6.1.6 ISR3, including the ability to more easily debug individual Monte Carlo sample points, adding user-defined columns to the outputs tables, more efficient use of disk space, and performance improvements.

15. Keeping Your Circuit in Tune: Sensitivity Analysis and CIrcuit Optimization

Gives an overview of how to use sensitivity analysis and circuit optimization in Virtuoso Analog Design Environment GXL (ADE GXL) to efficiently tune your circuit over corners and statistical variation.

16. What's New in Virtuoso ADE XL in IC616 ISR6?

Discusses new features in ADE XL in IC6.1.6 ISR6, including corner export/import to CSV, creation of K-sigma corners from Monte Carlo results, the ability to add user notes, cancelling selected tests and corners, and value-based statistical corner creation.

Support and Documentation

17. Cadence Online Support Release Highlights

Describes recent enhancements to the Case Creation Pages and Design IP Email interface.

18. FAQs and Quick Start Guides added to the Virtuoso IC 6.1.6 documentation set

The following documents have been added or updated in various IC6.1.6 ISRs to supplement the existing Virtuoso documentation set. They cover a range of topics including FAQs, Quick Start Guides, and process flow information for particular product areas.

• Pcell IDE - Quick Start Guide (added in IC6.1.6ISR5 release)
• SKILL IDE Developer's Quick Start Guide (added in IC6.1.6ISR5 release)
• Virtuoso Schematic Editor - Productivity Shortcuts (added in IC6.1.6ISR3 release)
• Virtuoso Fluid Guard Ring Frequently Asked Questions (added in IC6.1.6ISR5 release)
• Virtuoso Quick Start:Virtuoso Floorplanner Flow (updated in IC6.1.6ISR3 release)
• Virtuoso Layout Suite L Frequently Asked Questions (added in IC6.1.6ISR6 release)
• RelXpert in ADE - Quick Start Guide (added in IC6.1.6ISR6 release)

19. How to turn on AMS UNL in IC 616 ISR6

The new AMS Unified Netlister (AMS UNL) was released in IC 6.1.6 ISR6.  Here's how to enable it.

Application Notes

1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40) LVS

Shows you how to put in place the PVS(LVS)-QRC(av_extracted) view using TSMC files.

Videos

2. Mismatch Contribution in Virtuoso Analog Design Environment GXL

Mismatch contribution analysis is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify the identified devices in the design to make the design less sensitive to device mismatch variation in IC 6.1.6.

Rapid Adoption Kits

3. Substrate/Well Connectivity Extraction

The substrate/well connectivity enhancements were made in VLS XL to help designers work more effectively on designs at lower geometry nodes.This RAK steps through the Extractor capabilities -- detecting short on a same substrate, creating isolated substrate and how to break a propagated connectivity on the same layer based on a generic 90nm PDK. IC6.1.6 ISR5

4. Making a layout XL-compliant using Update Binding (XLME)

Often layout engineers have existing or legacy layouts that they wish to use in VLS XL to take advantage of the connectivity-driven flow. With the introduction of the Update Binding functionality in IC6.1.6, it is now possible to quickly make a legacy layout fully XL-compliant.  IC6.1.6 ISR6.

5. Routing Constraint Interoperability - AoT Flow (Analog on Top)

This workshop demonstrates the capability to capture routing constraints in either Virtuoso or Encounter Digital Implementation System, propagate routing constraints across hierarchical boundaries, perform routing (using NanoRoute and the Virtuoso Wire Editor) while honoring constraints, and validate the routing results against the original routing constraints using PVS-cv. EDI 13.2 and Virtuoso IC6.1.5 ISR17.

6. Custom Digital Placement

The Custom Digital Placer is used to implement small digital designs with several thousand placeable components.  The Custom Digital Placer can also be used to place a few transistor-level devices along with standard cells (mixed mode).  IC6.1.6 ISR6

7. IC6.1.6 VSR ASIC Power and Signal Block-Level Autorouting Flow

This RAK steps through the power routing and signal routing of block-level stdcell ASIC flow.  IC6.1.6 ISR6.

8. Virtuoso Floorplanner Flow

This RAK steps thorugh the Floorplanner Flow in Virtuoso IC6.1.6 ISR5. The objective of this flow is to increase layout productivity through improved floorplanner functionality aimed at block-level interconnect. 

9. Virtuoso Analog Auto Placer

This RAK demonstrates the steps to use the Analog Placer in Virtuoso IC6.1.6 ISR5. This does automatic constraint-based placement. We will explore different placement modes like Quick Placement, Automatic Placement (more compact), and Place Like Schematic.

10. Voltus-Fi EMIR Analysis Workshop

This workshop will take you through IR-drop and electromigration analysis flow utilizing our patent-pending technology in MMSIM (APS/XPS) followed by visualization of results in Virtuoso Layout Editor.  IC6.1.6 ISR6 and MMSIM13.1 ISR3.

11. Sample Pcells Abutment

This RAK steps through the pcell abutment in Virtuoso IC6.1.6 ISR6.The objective of this document is to illustrate setting up the pcell abutment using the different properties with Cadence default abutment code and using custom abutment function.

Blogs

12. High-Yield Analysis and Optimization -- How to Design the Circuit to Six Sigma

Discusses the methodology and algorithms in ADE GXL to perform high-yield estimation and six-sigma statistical corner creation to help meet high-yield requirements for memory design and other mission-critical applications.

13. How to Specify Phase Noise as an Instance Parameter in Spectre Sources (e.g. vsource, isource, Port)

Describes the new capability in MMISM 13.1 to specify phase noise as an instance parameter on Spectre sources. 

14. DAC 2014: 30+ Customer, Partner Presentations Now Available on Cadence.com

One of the busiest spots on the Design Automation Conference (DAC 2014) show floor was the Cadence Theater, which featured continuous customer and partner presentations over a three-day period June 2-4. These informal, half-hour presentations allowed engineers to learn about problems and solutions from other engineers, and to hear about the latest capabilities from Cadence ecosystem partners. Most of the Cadence Theater presentations are now available in the form of audiotapes and slides.

Solutions

15. How to stop popup of Distributed Processing Options Form

For users of ADE Distributed Processing, a few key environment variables for those popup haters out there. 

16. Information, Q&A on APS parasitic reduction: +parasitics and ++parasitics options

 Nice one-stop shop for information about what these options do and how to use them.

17. How is mismatch applied in array/parallel devices in Spectre Monte Carlo?

Important information about the way mismatch is handled for different types of device configurations. 

18. How to perform a stability (stb) analysis on a loop within an extracted view

Clever little trick to facilitate analyzing loop stability on post-layout designs.

19. Verilog Netlisting (Verilog Out): Quick Reference to Basics and Frequently Referred Solutions

 Handy document on Verilog netlisting with lots of useful links to extra information.

20. auCdl Netlisting of schematic: Quick Reference to Basics and Frequently Referred Solutions

Handy document on auCdl netlisting, usually used for LVS.  Lots of links to extra information.

21. SPICEIN: Quick Reference to Basics and Frequently Referred Solutions

Handy document on SpiceIn to import textual netlists (CDL, HSpice, Spectre, SPICE) and create either schematic or netlist views. 

Stacy Whiteman

Excuse the tennis analogy, but just coming out of Wimbledon!  However, EDA and academia have had a long-standing tennis match, if you will, in which there is a "give and take"  between the EDA world and the many universities around the world. At Cadence, we have an extensive University Program and, through the years, we have worked closely on everything from developing curriculum (using our software, of course) to engaging universities in specific research for us to assisting Ph.D. students with the work on their theses. In fact, the Design Automation Conference (DAC) has had a university arm from the earliest days of the conference. This brings me to the reason for this blog, to congratulate Carnegie Mellon University Ph.D. student Shupeng Sun for receiving  the newly established Best Poster Award at the ACM SIGDA Ph.D. Forum at this year's DAC in San Francisco. The poster focused on Sun's radically new statistical analysis methodology that will allow companies to produce better circuits in electronic devices.

The reason it is of particular interest to me is that the work was a collaborative project between CMU and Cadence. A number of Cadence researchers and developers also have been involved in the project, including engineering directors Hongzhou Liu and Ben Gu, and Kangsheng Luo, a senior member of the technical staff.

All electronics are made up of thousands or even millions of circuit blocks, each of which can contain thousands of transistors — and if one of these blocks fail, the electronic device will not function properly. As electronics become more complicated, more circuit blocks are needed, increasing the chance for failure.

"If you only have 10 circuit blocks, it is relatively easy to make all 10 work, but if you have one million circuit blocks, then it is more difficult to make all of them work," said ECE Associate Professor Xin Li, Sun's adviser and research colleague.

Before Sun's novel work, validating a circuit block involved running a computer simulation that produces sample circuit blocks. Each sample can take minutes to hours to simulate, and millions of samples are required for an accurate validation of a new design. This method is very costly because it can take a few weeks or months to run one validation. And if the original design does not work, a second validation must be run — an enormous problem if a circuit designer has a deadline. Because the simulation process is so laborious, most companies opt for a very simple, very inaccurate estimation.

Sun developed an algorithm that calculates the failure rate and accounts for variability and uncertainties in the manufacturing process, allowing companies and researchers to run significantly fewer simulations. This new statistical methodology, referred to as Scaled-Sigma Sampling (SSS), requires producing only a few hundred or thousand samples.

"A few of the world's top semiconductor companies are already evaluating this new algorithm, and we are in the process of integrating it with our commercial product, Virtuoso ADE GXL," said Glen Clark, vice president of R&D for Cadence. "This is a great example of how a university and an EDA company can work together to deliver innovative solutions for the challenging problem of memory circuit yield."

Working collaboratively with universities has been a hallmark of Cadence, and we look forward to many more interesting and fruitful adventures together. I wonder if that is what Federer said to Djokovic when they shook hands across the net?  Congrats all around.

Steven Lewis 

Apologies for skipping a month, but things got a bit hectic, so enjoy a double-dose of browsing today.

Application Notes

1. Cadence Online Support Release Highlights

New features for searching and filtering, viewing cases and providing feedback

2. Generic Process Design Kit Downloads 

Get the latest versions of the Cadence Generic Process Design Kits (GPDK) and standard cell reference libraries, which are provided for use with Cadence Design Tools and Flows of Virtuoso and Encounter products. They are intended to be representative of actual semiconductor process.

3. Exchanging OA Database Views between Encounter (EDI) and Virtuoso (IC)

Talks about the basic things to know when interoperating between Encounter and Virtuoso for doing Analog-on-Top or Digital-on-Top design.

4. AMS Supply-Sensitive Connect Modules Application Note

Supply-sensitive connect modules offer a way to cleanly and accurately handle analog-to-digital and digital-to-analog conversion in analog/mixed-signal circuits involving multiple supplies and multiple voltages (MSMV).  This document provides multiple examples of how to implement this functionality.

5. Cadence Licensing FAQ

Compact presentation of the mostly frequently asked questions (and answers) to customer support regarding licensing.

6. Dongle Installation

How to set up Cadence licensing using USB dongles.

7. Layout Enhancements in IC6.1.6 ISR7 and ICADV12.1 ISR9

Describes new layout functionalities in the areas of Creating/Editing, Object Selection cycling, Copy/Move mirroring, Via Generation, Cloning, virtual connection and hierarchical extraction from selected instances.

8. Creating Batch Triggers in PVS

How to set up pre- and post- triggers from the Virtuoso GUI environment to perform various tasks before or after a PVS run.

Videos

9. Creating Pad Ring using Power Router

This video demonstrates how to create Pad routes using Power routing GUI in Virtuoso and save routing schemes for future use. It also shows SKILL rtePowerRoutePadRing command that can be used instead of GUI approach.

10. Introduction to Customer Support

Lots of great information about how to be more effective in using http://support.cadence.com.  Plus male AND female computer voices.

11. Modgen ECO Methodologies

Covers how to update Modgen constraints after device or constraint parameters have been updated in the schematic, and how to update the constraint view with Modgen changes made in the layout view.

12. New Features in SimVision 14.1 Release

Covers Driver tracing enhancements, Schematic Tracer, UVM and RTL Debug and other ease-of-use enhancements.

Rapid Adoption Kits

13. PLL Verification Workshop

Detailed workshop demonstrating different methods of characterizing PLL's and their principal components. 

14. Using VEC and VCD Files in AMS and Analog Simulation in ADE

Explains (and walks through) how to use digital stimulus (VCD, EVCD and VEC) files in AMS simulation with Spectre/Ultrasim as the analog solver.

15. Statistical Analysis

Demonstrates features of ADE XL and ADE GXL to perform Monte Carlo analysis, create fast K-sigma statistical corners and use circuit optimization to tune design performance and improve circuit yield.

16. Layout Design in IC6.1.6

Basics of using the Virtuoso Layout Suite, updated for IC6.1.6 ISR6.

17. Electrically Aware Design (EAD) Worskhop

EAD allows extraction of layout parasitics at any arbitrary point in a design cycle, including parasitic resimulation and electromigration analysis.  Updated for IC6.1.6 ISR7.

Blogs

18. Voltus-Fi Custom Power Integrity Solution: Electromigration and IR Drop at the Transistor Level

Introduces Cadence's new tool which provides transistor-level electromigration and voltage drop analysis with foundry-certified SPICE accuracy.

19. Quantus QRC Extraction Solution -- Massive Parallelism Extracts Accurate Parasitics Quickly

Introduces Cadence's release of a next-generation parasitic extraction tool that leverages massive parallelism to deliver up to 5X faster turnaround time.

20. EDA Plus Academia: A Perfect Game, Set and Match

Well-deserved kudos for collaborative research between Carnegie Mellon University and Cadence on a radically new statistical analysis methodology which won the newly established Best Poster Award a the ACM SIGDA Ph.D. Forum at this year's DAC.

Stacy Whiteman

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. You can also compare the relative importance of the contributing instances.  The analysis results can aid in making design changes to reduce the variation.  Mismatch Contribution is a variance-based global sensitivity analysis ^[1].

Mismatch Contribution is launched from Monte Carlo results.

 Here is a flat view of the outputs, and mismatch parameters are displayed and sorted by the swing specification.

Each device instance may be modeled with multiple statistical mismatch parameters.  The parameter names themselves are not always of interest.  In some cases the PDK models are derived from principal components.  Mismatch Contribution provides a hierarchical view where the total contribution of all of the device parameters is displayed for each instance.  The hierarchical view reports the contributions by instance for quick identification of important instances.

Cross probing to the schematic is provided.  The schematic is opened to the same level of hierarchy, and the selected instances are highlighted.  Navigate the table as you would a schematic.  Descend into a row (instance) of the table until reaching the leaf level.  The leaf level again displays the individual mismatch parameters of the instance.

By contrast, a top-level view with four blocks shows the block contributing the most variation of the specification.  Descend to find the lower-level contributors.

When global process variation is applied during the Monte Carlo analysis, the contributions from the process parameters are included in the contribution analysis.

Mismatch Contribution is not limited to linear effects.  When a linear model of the data is insufficient, a quadratic model is automatically applied.  The R^2 value in the header of the table for each specification is the proportion of variance explained by the model.  This is the goodness of fit of the model.  Sparse regression techniques allow for computation of the contributions even when the number of parameters is very large compared to the number of Monte Carlo samples simulated ^[2].

Mismatch Contribution is available now in Virtuoso ADE GXL, first released in IC6.1.6 ISR3.

[1] http://en.wikipedia.org/wiki/Variance-based_sensitivity_analysis 
[2] J. Tropp and A. Gilbert, "Signal recovery from random measurements via orthogonal matching pursuit," IEEE Trans. Information Theory, vol. 53, no. 12, pp. 4655--4666, 2007.

Lorenz Neureuter

Development Model for ADE and ViVA

Virtuoso Analog Design Environment (ADE) and ViVA follow a development model that allows new content to be added in every third ISR.  These content ISRs receive additional usability testing, product validation, and demonstrations and beta testing with customers. This development model gives R&D long enough development cycles to add meaningful content while ensuring that quality and stability of the main ISR stream is not compromised.

While this development model provides an excellent method to deploy new features and functionality in a frequent but controlled manner, it also presents challenges in making customers aware of the new capabilities.  This blog post outlines some of the new features that first appeared in ISR 3, which was released in November (hence the "-ish" in the blog title).  The next content release, ISR 6, will be available at the end of April so look for a fresh post with additional new items soon.

So let's get too it!  What's New(-ish) in ADE XL in 616 ISR 3?

• Performance and stability improvements when working with a large number of corners
• Better handling of disk full and other conditions which previously resulted in crashes
• Usability improvements in Annotation Balloons based on user feedback
• Ability to add user defined columns in ADE XL outputs setup and results table
• Allowing individual ICRP processes to be stopped and resubmitted
• Improved error debugging and access to job log
• Setting default results view for single run, sweeps and corners
• Measurements tied more tightly to analyses
• Improved use model for pre-run scripts
• More efficient use of disk space when a netlist is re-used for all points
• Low Discrepancy Sequence (LDS) sampling method support for Monte Carlo
• Ability to launch Debug Environment for Monte Carlo points
• Sample points displayed on histograms with cross selection to ADE XL results table

What new feature are you most excited to see?  Are there other features that you would like to have to make your job easier?  Do you have questions about ADE XL or other Virtuoso products?  Leave a comment  below and I will try to address them in future blog posts.  Also watch this space for details about new features in ISR 6 when it is released at the end of the month.

Tom Volden

Highlights for this month include lots of useful Physical Verification System (PVS) appnotes and several blog articles on advanced analyses and flows in Analog Design Environment (ADE) GXL.

Application Notes

1. Physical Verification Checks and Generic Tips

Concise overview explaining the basics of the various DRC and LVS checks in rules files.

2. Recommendations and Tips for the PVS DRC Flow

Includes sections on preparation of runsets, running DRC, preparation of design blocks and DRC/LVS check of top-level GDS.

3. Recommendations and Tips for the PVS LVS Flow

Design and runset preparation, links to helpful solutions and sources of common errors.

4. Recommendations and Tips for the PVS Metal Fill Flow

Preparation of runsets, working with different fill scenarios and how to correct errors.

Rapid Adoption Kits

5. Making a layout XL-compliant using Update Binding (XLME)

Uses a sample design scenario to explain how the Update Binding command can be used to increase the VLS XL-compliance of a design using the physical connectivity in the layout and the output from a PVS LVS run. 

6. PSPICE netlist support in ADE

Describes the integration support in Analog Design Environment (ADE) to include a netlist in PSPICE format.

Solutions

7. Why isn't there an hbxf in the Choosing Analyses form?

You have recently started using the GUI for hb analysis and the associated small signal analyses. You noticed that there is a periodic xf (pxf) small signal analysis for pss. Why isn't there a similar analysis (hbxf) for hb?  Click on the link to find out.

8. Is PSF-XL supported for AMS simulation?

(Spoiler Alert) Why yes.  Yes it is.  This solution will tell you how to use this faster analog waveform format. 

9. Why do we have mulitple MMSIM13.1 hotfixes on downloads?

Several MMSIM 13.1 hotfix versions are being maintained on downloads to accommodate specific foundry/PDK rollouts.  Click the link for more information.

10. How to create a form showing a thumbnail image of the cellView

Wow, this could be fun.  A while ago, I wrote an article about how to create thumbnail images.  Now you can find out how to include those images in your own forms.

11. Does bindkey work with forms?

This solution provides an example of how to create a form in which you can register your own set of bindkeys.

12. How to create a custom RAP generator that creates additional constraints?

I would like to modify the existing CurrentMirror generator code to create additional constraints, for example, orientation and matched parameter constraints in addition to the modgen constraint. Here is that sample code.

Blogs

13. Fast Yield and Statistical Corners

Describes the different sampling methods available in ADE XL Monte Carlo analysis, the advantages of using auto-stop if you don't know how many samples are needed, and the types of statistical corners that can be created from the Monte Carlo results to help the designer improve circuit yield.

14. Efficient Design Migration Using Virtuoso Analog Design Environment GXL

The article provides an overview of a methodology for performing process migration for schematics and testbenches, including PDK and design assessment, design migration and final verification.

15. Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. The article describes the concepts behind this analysis how to use it.

Stacy Whiteman

Anyone who has ever played a musical instrument knows how hard it can be to keep the instrument in tune when subjected to variations in weather conditions. Heck, in 2009, Yo-Yo Ma and friends (sorry, he gets top billing because I used to play the cello) pantomimed their performance at the Presidential Inauguration because their instruments wouldn't function properly in the frigid temperatures. Guess they didn't want to risk sounding like my seventh-grade orchestra in front of that large an audience. 

Well, we've been talking a lot in this blog recently about the problems caused by the effects of variation on circuit design, and the risks of being "out of tune" can be just as great when it means your chip is late or doesn't work properly.

• How to sort through hundreds of combinations of PVT corners to find the ones that really matter
• How to efficiently analyze and design across statistical process and mismatch variation
• How to smoothly migrate a design from one process node to another while maintaining circuit performance
• How to quickly identify which parts of the circuit to tweak so statistical mismatch effects won't throw your design out of spec

Today we're going to talk about some of the features available in the Virtuoso Analog Design Environment GXL (ADE GXL) to help you tune your circuit to overcome the effects of variation on circuit performance. Let's start by putting things in the context of an overall flow that looks like this:

Setup and Corner Creation

The basic idea here is that you start with a test setup in ADE XL, which can consist of multiple testbenches, each with a set of output measurements and design specifications. Then you add the relevant corners, which will cover the limits of the design performance across which you need to optimize. These can be your standard PVT corners, they can be a critical subset of corners generated using the ADE GXL Worst Case Corners analysis, or they can be statistical corners generated from a Monte Carlo analysis to capture 3-sigma or other outlying statistical behavior for each of your design specifications. 

Parameterization

One of the keys to getting the most out of the circuit-tuning capabilities in ADE XL and ADE GXL is device parameterization. I've written about this feature before, but to recap, the Variables and Parameters Assistant in ADE XL allows you to create parameters for any device properties and vary them at will without having to edit the schematic. You can also incorporate critical device matching and ratioing relationships. 

The "Create Parameter Range" option will automatically create a +/-% range on any parameters, which makes sensitivity analysis and optimization a snap.

Sensitivity Analysis

Sensitivity Analysis in ADE GXL allows you to get a good idea of the criticial devices in your circuit and their effects on design performance. With only a few targeted simulations, you can find out which devices in your circuit have the most impact on each of your design specifications, as well as how changing a device size whether changing a device size to improve one spec will adversely change the other specs.  Device parameterization makes it quick and easy to evaluate "what-if" scenarios until your desired performance is achieved.

Local and Global Optimization

The optimization algorithms in ADE GXL have been proven within our customer base for many years. The optimizer works across all the multiple testbenches, specifications, and corners you already have set up, including the worst-case PVT and statistical corners you have defined to capture the extreme boundaries of your circuit behavior. Device parameters are intelligently varied over the ranges you have defined until all design specifications have been met. Simulations are distributed using ADE XL's job distribution system to maximize the efficiency of the analysis.

ADE GXL provides four local optimization algorithms: BFGS (recommended for most common analog circuits), Conjugate Gradient, Brent-Powell, and Hooke-Jeeves. Use these when you have a reasonable degree of confidence in your initial circuit starting point values. If you aren't sure of your starting point, use Global Optimization, which will perform a much broader exploration of the design space to find viable circuit solutions.

Several additional optimization-based run modes are available, including Size Over Corners to efficiently optimize over a large number of corners and Improve Yield, which combines Monte Carlo analysis and automatic statistical corner creation with iterations of circuit optimization to center your design within statistical process and mismatch variation.

Verification

"The proof of the pudding", as they say, "is in the eating," so the final step in our big red PowerPoint SmartArt arrow above is to verify the results of the circuit tuning. This may involve running a final simulation across all PVT corners or a final Monte Carlo analysis to verify the optimized design can overcome the effects of all types of variation.

In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3.  Here are more new features that are now available in Virtuoso ADE XL in the recently released ISR6.

• Notes can be added to tests, variables, corners, parameters, and histories. This allows you to document information about important items in your setup or make notes about a particular history to document simulation conditions, results, or other key information.
• Comma separated value (CSV) files can now be used to import and export corners setup. This improves the use model for managing corner setups in external editors. Prior to this enhancement, import/export required the use of more complicated XML format from the Virtuoso ADE XL setup database (SDB).
• Ability to cancel selected tests and corner points. Previously, stopping a run canceled all running and pending simulations. The new feature allows you to selectively cancel individual simulation for a particular corner or test. Remaining tests and corners will continue to be run.
• Creation of K-sigma corners from limited Monte Carlo samples. The new algorithm estimates the Probability Density Function and computes the corner specification value based on that PDF. A statistical corner that matches the target specification value is then created. This is an improvement over previous methods for creating statistical corners with a particular standard deviation as they required a large number of Monte Carlo points to achieve accurate results.
• Ability to filter evaluation and simulations errors from yield estimate in Monte Carlo simulations
• Wild card selection is now supported in the Annotation Setup form
• Value-based statistical corner creation from Monte Carlo simulation is available. This allows the distribution point to be maintained with minor changes to the design such as addition of new device instances. Prior to this, any changes to the design which impacted connectivity would invalidate the statistical corner.

What new feature are you most excited to see?  Are there other features that you would like to have to make your job easier?  Do you have questions about Virtuoso ADE XL or other Virtuoso products?  Leave a comment  below and I will try to address them in future blog posts.

Tom Volden