The IC6.1.7 ISR22 and ICADV12.3 ISR22 production releases are now available for download. To find out more, click here…(read more)![]()
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Virtuoso IC6.1.7 ISR22 and ICADV12.3 ISR22 Now Available
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Virtuosity: Opening Old ADE States and Views with ADE Explorer and ADE Assembler
Have you found it a pain that when opening a Virtuoso ADE L state or a Virtuoso ADE XL view that the default application is still the old ADE L or XL? If you've moved on to Virtuoso ADE Assembler or Virtuoso ADE Explorer world then you need to change the application in the Open File dialog to ADE Explorer or ADE Assembler.
To set the application by default we have added a couple of environment variables that you can set in your .cdsinit or .cdsenv files.(read more)![]()
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Virtuosity: What Did I Miss in Virtuoso Visualization and Analysis and ADE during the IC6.1.7/ICADV12.3 ISRs?
Maybe you've been stuck on a project that used an older version of Virtuoso, maybe you've just subscribed to these blogs or maybe you're a new user to Virtuoso and perhaps you don't know about the new cool features that have been added over the course of the IC6.1.7/ICADV12.3 ISRs. We have packed a huge amount of enhancements in, the count is over 1600!
I can't detail all of them here, but I'll outline the major enhancements in Virtuoso ADE Assembler, Virtuoso ADE Explorer and Virtuoso Visualization and Analysis, and provide links to where you can find out more.(read more)![]()
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Virtuosity: Doing Placement in a Row-Based Environment
At advanced nodes, Virtuoso provides the capability of defining row templates and generating row regions in the layout design. You can then use the automatic and assisted placement options to place devices, Modgens, and standard cells in these rows. (read more)![]()
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Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?
This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing IR drop and EM currents in the Virtuoso ADE environment. The Spectre EMIR/Voltus-Fi XL flow provides many advanced features, such as static EMIR, Static Power Grid Solver (SPGS) point-to-point resistance checking, power gate handling, signal net IR drop, differential IR drop, what-if analysis, and self-heating analysis. In addition, Spectre EMIR analysis provides powerful options for optimizing EMIR accuracy and performance. The blog refers to documents, and workshops that provide detailed descriptions and illustrations about Spectre EMIR solution.(read more)![]()
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Virtuoso IC6.1.7 ISR23 and ICADV12.3 ISR23 Now Available
The IC6.1.7 ISR23 and ICADV12.3 ISR23 production releases are now available for download at Cadence Downloads.
For information on supported platforms, compatibility with other Cadence tools, and details of issues resolved in each release, see:
The links above are functional at the time of publishing. If you encounter any links that are now obsolete, visit https://downloads.cadence.com and select the release name you are interested in to access the related files.
Here is a listing of some of the important updates made to IC6.1.7 ISR and ICADV12.3 ISR over the last few releases:
- Faster Netlist Generation for Analog Components in a Mixed-Signal Design (from ISR22)
Use the new Create spectre subckt for extracted view check box to generate an optimized netlist for analog components in a mixed-signal design. Not only does the new option improve the netlisting performance but it also skips the mixed-signal elaboration step for these cellviews, saving the overall simulator processing time. - Default Application to Open a Saved ADE State (from ISR21)
Specify the default application where you want to open a saved ADE state. Use these while migrating to ADE Explorer or ADE Assembler. - Wildcard Syntax for Saving PCells in Netlist (from ISR21)
Use wildcards to specify PCell operating point parameters on the Save Options form.
For more details on these and all the other new and enhanced features introduced in this release, see:
Contact Us
Please send questions and feedback to virtuoso_rm@cadence.com.
To receive Virtuoso release announcements like this one, and other Virtuoso-related information, directly in your mailbox, type your email ID in the Subscriptions field at the top of the page and click SUBSCRIBE NOW.
Virtuoso Release Team
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Virtuosity: Saving Time, Effort, and Money with Express Pcells
Use the Express Pcell feature and see for yourself how you can save time, effort, and money!(read more)![]()
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Accurate Pin-to-Pin Resistance Modeling for Wide, Slotted Metal Structures using Advanced Adaptive Mesh Extraction Technology in Quantus
In Analog/RF layouts, designers frequently use slotted metal structures. Such slotting is done either to satisfy DRC requirements from foundries to satisfy max. density rule criteria, or to reduce eddy current losses in return paths of a transmission line/coiled spiral inductor. Current flow in such slotted metal structures is non-uniform, hence, traditional parasitic extraction approaches with predefined fracture length specifications do not result in accurate pin-to-pin resistance. Hence, Cadence Design Systems sign-off extraction solution – Quantus, provides a mesh extraction approach for these cases, where the slotted/wide metal structures are broken down into smaller squares each representing a small parasitic resistance. This approach of moving from a lumped to distributed model for resistance extraction leads to much better DC V/I current modelling. For example, the MIMCAP layout structure shown below has its 2 terminals ctm (top) and cbm (bot), connected to Metal 13 for its VSS and VDD connections. Its ESR (Effective Series Resistance) is calculated at 50GHz by doing an AC V/I simulation.
Image Source: PVS Quick View Editor
ESR @ 50GHz with regular square counting based extraction is 19.04 ohms (incorrect), whereas by using advanced adaptive mesh gives 5.16 ohms (correct). The MIMCAP structure has very wide top and bottom terminals which needs to be modeled using mesh approach to give accurate results. However, the challenge with this approach is increased netlist size, simulation run time and user overhead in setting up the mesh layers and corresponding mesh sizes to be extracted.
Quantus has newly introduced advanced adaptive mesh extraction, where intelligent meshing is applied to automatically detect non-uniform current regions near discontinuous/slotted metal structures where adaptive grid meshing is applied and detect uniform current regions near continuous metal structures where square counting-based meshing is applied.
The below case study is performed on a ST BiCMOS 55nm process. However, the advanced adaptive mesh technology can be applied to other advanced technology nodes too with similar benefits.
Image Source: Cadence Virtuoso Layout Editor
Adaptive mesh fractured the M1 slotted ground plane by using smaller fracture regions even in right most regions of the layout structure, where there are no slots and current flow is uniform. Whereas, the new Advanced adaptive mesh (available in latest Quantus builds) was able to automatically distinguish between the slotted and continuous metal regions and apply intelligent meshing only near the slotted metal portion, where current flow would be non-uniform and distributed modelling is required. Also, in Advanced adaptive mesh, the size per mesh is 5.96x5.96 which is larger than the 2.59x2.59 determined automatically in Adaptive mesh. Since each fractured square region corresponds to 1 parasitic resistor, this helps reduce the total number of parasitic resistors. A combination of these 2 techniques, helped reduce the netlist size dramatically by ~34%.
In cases where only a certain region of the layout structure needs distributed modelling, meshR user region can be defined, so that Quantus performs advanced adaptive or adaptive meshing in only a certain portion of the layout, whereas the remaining would be square counting based fracturing approach. This further helps reduce netlist size.
The reduction in number of parasitic R and C’s in the advanced adaptive mesh netlist as a result can speed up downstream simulation run time while consuming lesser memory. Its critical to also ascertain the accuracy of the reduced netlist wrt. adaptive mesh to confirm the reduction doesn’t come at the cost of accuracy. Hence, a pin-to-pin DC resistance check is performed on few fractured sub-nodes from the 2 DSPF netlists, keeping in mind the sub-nodes are picked with roughly similar x,y coordinates. Advanced adaptive mesh can also be applied to spice extracted view output formats. As demonstrated, pin to pin resistance accuracy in advanced adaptive mesh is highly accurate.
Depending on the level of simulation accuracy needed, there is a capability to specify a k-scaling factor to increase or decrease the auto mesh size. This helps fine tune the netlist size vs. simulation accuracy desired.
The Adaptive Mesh feature is based on the user-specified mesh size for the conductor layers that are to be meshed. Alternatively, Advanced Adaptive Mesh feature is based on automatic mesh sizing for the conductor layers. Thus, setup and usage of Advanced adaptive mesh is simpler for these users. With the advent of advanced nodes and slotted layout structures, distributed MIMCAPs designs and other newer design artifacts, it is recommended to use the Advanced adaptive mesh solution in Quantus to achieve better netlist size, accuracy and simulation run times.
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Virtuosity: Updated ADE Assembler and ADE Explorer Rapid Adoption Kit
The Virtuoso ADE Assembler and Virtuoso ADE Explorer Rapid Adoption Kit (RAK) has been updated for IC6.1.8/ICADVM18.1 to cover the new features. These include
Setup Library Assistant
Worst Case Corners in Run Plan
Minor usability improvements(read more)![]()
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Accurate Pin-to-Pin Resistance Modeling for Wide, Slotted Metal Structures Using Advanced Adaptive Mesh Extraction Technology in Quantus
In Analog/RF layouts, designers frequently use slotted metal structures. Such slotting is done either to satisfy DRC requirements from foundries to satisfy max. density rule criteria, or to reduce eddy current losses in return paths of a transmission line/coiled spiral inductor. Current flow in such slotted metal structures is non-uniform, hence, traditional parasitic extraction approaches with predefined fracture length specifications do not result in accurate pin-to-pin resistance. Hence, Cadence Design Systems sign-off extraction solution – Quantus, provides a mesh extraction approach for these cases, where the slotted/wide metal structures are broken down into smaller squares each representing a small parasitic resistance. This approach of moving from a lumped to distributed model for resistance extraction leads to much better DC V/I current modelling. For example, the MIMCAP layout structure shown below has its 2 terminals ctm (top) and cbm (bot), connected to Metal 13 for its VSS and VDD connections. Its ESR (Effective Series Resistance) is calculated at 50GHz by doing an AC V/I simulation.
Image Source: PVS Quick View Editor
ESR @ 50GHz with regular square counting based extraction is 19.04 ohms (incorrect), whereas by using advanced adaptive mesh gives 5.16 ohms (correct). The MIMCAP structure has very wide top and bottom terminals which needs to be modeled using mesh approach to give accurate results. However, the challenge with this approach is increased netlist size, simulation run time and user overhead in setting up the mesh layers and corresponding mesh sizes to be extracted.
Quantus has newly introduced advanced adaptive mesh extraction, where intelligent meshing is applied to automatically detect non-uniform current regions near discontinuous/slotted metal structures where adaptive grid meshing is applied and detect uniform current regions near continuous metal structures where square counting-based meshing is applied.
The below case study is performed on a ST BiCMOS 55nm process. However, the advanced adaptive mesh technology can be applied to other advanced technology nodes too with similar benefits.
Image Source: Cadence Virtuoso Layout Editor
Adaptive mesh fractured the M1 slotted ground plane by using smaller fracture regions even in right most regions of the layout structure, where there are no slots and current flow is uniform. Whereas, the new Advanced adaptive mesh (available in latest Quantus builds) was able to automatically distinguish between the slotted and continuous metal regions and apply intelligent meshing only near the slotted metal portion, where current flow would be non-uniform and distributed modelling is required. Also, in Advanced adaptive mesh, the size per mesh is 5.96x5.96 which is larger than the 2.59x2.59 determined automatically in Adaptive mesh. Since each fractured square region corresponds to 1 parasitic resistor, this helps reduce the total number of parasitic resistors. A combination of these 2 techniques, helped reduce the netlist size dramatically by ~34%.
In cases where only a certain region of the layout structure needs distributed modelling, meshR user region can be defined, so that Quantus performs advanced adaptive or adaptive meshing in only a certain portion of the layout, whereas the remaining would be square counting based fracturing approach. This further helps reduce netlist size.
The reduction in number of parasitic R and C’s in the advanced adaptive mesh netlist as a result can speed up downstream simulation run time while consuming lesser memory. Its critical to also ascertain the accuracy of the reduced netlist wrt. adaptive mesh to confirm the reduction doesn’t come at the cost of accuracy. Hence, a pin-to-pin DC resistance check is performed on few fractured sub-nodes from the 2 DSPF netlists, keeping in mind the sub-nodes are picked with roughly similar x,y coordinates. Advanced adaptive mesh can also be applied to spice extracted view output formats. As demonstrated, pin to pin resistance accuracy in advanced adaptive mesh is highly accurate.
Depending on the level of simulation accuracy needed, there is a capability to specify a k-scaling factor to increase or decrease the auto mesh size. This helps fine tune the netlist size vs. simulation accuracy desired.
The Adaptive Mesh feature is based on the user-specified mesh size for the conductor layers that are to be meshed. Alternatively, Advanced Adaptive Mesh feature is based on automatic mesh sizing for the conductor layers. Thus, setup and usage of Advanced adaptive mesh is simpler for these users. With the advent of advanced nodes and slotted layout structures, distributed MIMCAPs designs and other newer design artifacts, it is recommended to use the Advanced adaptive mesh solution in Quantus to achieve better netlist size, accuracy and simulation run times.
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Virtuosity: What's New in Run Plan – Part III
After two interesting blogs by Yagya Mishra that explained the most popular features of the Run Plan assistant in Virtuoso ADE Assembler , I am writing this third blog in the series to share with you the latest features introduced in the IC6.1.8 and ICADVM18.1 releases.(read more)![]()
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Spectre Tech Tips: Optimizing Spectre APS Performance
This blog discusses how to optimize the Spectre APS performance for analog and mixed-signal designs. It introduces the key options for adjusting simulation accuracy and performance, provides solutions for typical setup problems causing performance issues, and delivers tips on advanced methods for optimizing simulation performance.(read more)![]()
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Virtuosity: Introducing the Pin Tool
The Pin Tool follows an object-based approach to working with pins by consolidating and redefining the tasks under one umbrella. Various pin-related tasks are grouped in a logical design flow in the various menus in the Pin Tool. The tool includes several new options that let you perform a wide range of pin-related tasks.(read more)![]()
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Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction
An important requirement for project sign-off is to ensure that all the design simulations in ADE Assembler are run using the efficient (or pre-defined) sets of operating conditions (corners, sweeps, model files and so) in accordance to the project. ADE Assembler and ADE Verifier now allow you to plan and create project-specific master setups that you can use to create setups for individual tests in ADE Assembler. This enables quick and efficient setup creation at the test level. While Verifying the top-to-down progress of your design using ADE Verifier, you can compare the implementation histories with defined operating conditions from master setup and review the progress of your design based on Analog Coverage percentage reported by ADE Verifier. This blog briefly describes the value of Setup Library Assistant in ADE Assembler and ADE Verifier.(read more)![]()
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Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available
The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download. (read more)![]()
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Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further!
Cutting-edge innovation…Top-down planning…Reliableand formalized verification…Scalable performance!
These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the new release of Virtuoso® ADE Verifier in IC6.1.8 and ICADVM18.1. Analog verification methodology is ever-changing. With the introduction of very large and complex verification project setups involving multiple users, the verification standards and market pressure require much more from the software. Verifier is a comprehensive application that performs plan-based verification of analog and mixed-signal designs. The latest IC release of Verifier brings much anticipated improvements that any verification manager will relish.
The internal architecture for Verifier has been upgraded to take performance, speed, and verification to the next level. The illustration below describes the high-level data structure of the new Verifier flow.
To support these architectural enhancements, we have made the following improvements:
- Performance: Improved performance enables faster verification of larger and more complex designs.
- Simulation Planning and Coverage Environment: Introduction of the Setup Library Assistant (SLA) in ADE Assembler and ADE Verifier enables planning and creation of project-specific master setups. In ADE Assembler, you can quickly and efficiently create setups at the test level using these master setups. In ADE Verifier, you can verify the top-to-down progress of your design by comparing the implementation histories with defined operating conditions from the master setups and reviewing the progress of your design based on the reported Analog Coverage percentage.
- Cellview Updates: On-demand updates, file based-monitoring, and the absence of update loops help in increasing performance.
- Sharing of Data: Direct sharing of data with ADE Assembler is now possible.
- UI Responsiveness: More responsive UI with intuitive forms, menus, and toolbars make the interface more user-friendly than ever.
- External Cellviews: Refashioned external reference flow to support unidirectional references to multiple Verifier cellviews provides a multi-level hierarchy, allowing more flexibility for designers, and the latest verification status to the project manager.
- SKILL Functions: New and improved task-oriented SKILL functions are now available.
- Flows: Improved flows for new assistants and filters, together with flows for exporting and importing CSV, Excel, and mapping files.
Try out the brand-new Verifier in IC6.1.8 and ICADVM18.1 to know how you can do more with your design project verification!
Related Resources
Rapid Adoption Kits
Videos
Blog
User Guides
For more information on Cadence circuit design products and services, visit www.cadence.com.
About Virtuosity
Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more… Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuosity posts.
Happy Reading!
Rashmi Girdhar
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Break the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET Design
How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda of Toshiba Memory (TMC) discloses his recipe today.(read more)![]()
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Virtuosity:"What's In a Name?"
It discusses the benefits of introducing tooltips in the Simulator Options and Analysis Options forms in Virtuoso ADE Explorer and Virtuoso ADE Assembler.(read more)![]()
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Virtuosity: Designing a Row-Based Layout Methodology – Why does this Make Sense at Advanced Nodes Today?
At advanced nodes, the complexity and volume of design rules have been growing exponentially. These challenges have contributed to the evolution of a row-based structured layout methodology, which lets you achieve a deterministic layout and increased layout efficiency.(read more)![]()
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Virtuosity: What Did I Miss in Virtuoso Visualization and Analysis and ADE during the IC6.1.7/ICADV12.3 ISRs?
Maybe you've been stuck on a project that used an older version of Virtuoso, maybe you've just subscribed to these blogs or maybe you're a new user to Virtuoso and perhaps you don't know about the new cool features that have been added over the course of the IC6.1.7/ICADV12.3 ISRs. We have packed a huge amount of enhancements in, the count is over 1600!
I can't detail all of them here, but I'll outline the major enhancements in Virtuoso ADE Assembler, Virtuoso ADE Explorer and Virtuoso Visualization and Analysis, and provide links to where you can find out more.(read more)![]()
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