At advanced nodes, Virtuoso provides the capability of defining row templates and generating row regions in the layout design. You can then use the automatic and assisted placement options to place devices, Modgens, and standard cells in these rows. (read more)![]()
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Virtuosity: Doing Placement in a Row-Based Environment
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Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?
This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing IR drop and EM currents in the Virtuoso ADE environment. The Spectre EMIR/Voltus-Fi XL flow provides many advanced features, such as static EMIR, Static Power Grid Solver (SPGS) point-to-point resistance checking, power gate handling, signal net IR drop, differential IR drop, what-if analysis, and self-heating analysis. In addition, Spectre EMIR analysis provides powerful options for optimizing EMIR accuracy and performance. The blog refers to documents, and workshops that provide detailed descriptions and illustrations about Spectre EMIR solution.(read more)![]()
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Virtuosity: In-design Electromigration Analysis - An efficient way to make layouts electrically correct
Shrinking size of ICs with highly complex layouts containing billions of transistors and miles of interconnects....all of this doesn't sound new now. The industry has been pretty fast in adopting advanced node designs and has witnessed various innovations to overcome the challenges faced at this level. One of the challenges is accurate and timely analysis of the effects of electromigration (EM) and IR drop, and faster clearance of physical verification of transistor-level designs. In-design electromigration analysis, a unique feature of Virtuoso Layout Suite, helps you address this challenge. Read more...(read more)![]()
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Virtuosity: A Smart Extracted View
The Cadence Quantus Smart View is the next generation of the Extracted View in the Virtuoso environment. The Smart View provides the same functionality as the Extracted View, but it uses a highly efficient and scalable storage mechanism. This means that Smart View can manage larger, more complex designs at advanced nodes with a reduced overall extraction run time and netlist size. In fact, the Smart View not only helps with faster netlist generation in Virtuoso ADE, you can also use it to view the parasitics in the layout within a desired threshold and also their net fragment names. You can also use the Smart View properties to analyze values and connectivity details of extracted parasitic elements.(read more)![]()
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Virtuosity: New Flexible Subwindows
Plots in Cadence Virtuoso Visualization and Analysis can be plotted in a window or subwindow. Subwindows allow you to see plots from different analyses side by side. Until IC6.1.8/ICADVM18.1, the subwindows were not very flexible. Now, we've improved these so that you can choose any grid layout of subwindows up to a 6x8 grid. In addition, you can resize the subwindows easily and move them around. These subwindow configurations are also stored as part of the Maestro Plotting Templates, which will be discussed in detail in an upcoming blog.(read more)![]()
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Spectre Tech Tips: Device Aging? Yes, even Silicon wears out
While most of us would like our electronic gadgets to last forever, the reality is that these gadgets have a lifetime. Most of the time, the lifetime of devices is limited by either mechanical (switch, relay), or thermal (fuse, capacitor) failures. However, as microchips designed in advanced technologies become more pervasive, the lifetime of microchips has become an additional issue.
Several effects contribute to device aging. Some effects, such as electromigration and Time-Dependent Dielectric Breakdown (TDDB) cause a sudden failure, while other effects, such as Hot Carrier injection (HCI) and Bias Temperature Instability (BTI), continuously degrade the performance with time.
As process feature sizes have scaled down, analyzing device reliability has become more complex as more and more phenomena contribute to the change in device characteristics. This is shown in the figure below.
There is one additional phenomenon (not shown in the figure), Time-Dependent Dielectric Breakdown (TDDB), which has impacted designers since the days of high-voltage linear analog. However, traditional CMOS process scaling rules helped avoid this issue until advanced node processes.
HCI Effect
HCI re-emerged as an issue as CMOS transistors scaled down into the deep submicron region. At shorter gate lengths, the electric field increases because power supply voltages don’t scale as fast as gate length scales down. The higher electric field in the channel leads to impact ionization collisions of electrons flow in the channel with the atoms in the lattice. These collisions generate hot electrons. Some of the hot electrons get trapped in the gate oxide. Electrons in the oxide increase the device threshold voltage and reduce mobility of electrons in the channel.
NBTI Effect
Negative Bias Temperature Instability (NBTI) occurs when positive carriers get trapped at oxide/silicon interface or in the oxide due to electrical stress when the voltage across the gate-source junction is negative. This effect is temperature dependent. NBTI is primarily an issue for PMOS transistors. The effect of NBTI increases when nitrogen is added to the oxide to reduce gate leakage current since less energy is required to create trap sites. Unlike HCI, which occurs gradually, NBTI has a more immediate impact. In addition, a partial recovery from NBTI can occur when electrical stress is removed and/or temperature drops. The NBTI is reversible when it happens in the bulk of the device, but it is permanent when the trapping occurs at the interface.
PBTI Efffect
Positive Bias Temperature Instability (PBTI) has become an issue with the adoption of Metal Gate High-K gate-stack technologies. NMOS transistors experience PBTI whose impact is temperature dependent. Unlike NBTI, interface traps are not created; therefore, full recovery is possible when the electrical stress is removed and/or temperature is lowered.
Spectre Native Reliability Analysis
You can use the Native Reliability feature of Spectre® to perform reliability analysis and address these effects with ease.
To perform reliability analysis, a prerequisite aging model should be available from the foundry. Some foundries use the Spectre® AgeMOS built-in model for Aging, while others use their proprietary model libraries to calculate the aging degradation for transistors.
Spectre® performs reliability analysis in two steps:
- In the first step, Spectre simulates the stress over the transistors and calculates the degradation based on the results of this simulation.
- In the second step, Spectre applies the degradation on the transistors to simulate the behavior of the circuit after the defined aging years.
Below is an example of a simple reliability statement to analyze the behavior of the circuit after 10 years of operation.
rel reliability {
age time=[10.0000y]
accuracy level=1
// Stress simulation
tran_stress tran stop=10u annotate=status
// Aged simulation
tran_aged tran stop=10u annotate=status
}
Related Resources
- Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre Extensive Partitioning Simulator (XPS) User Guide
- Spectre RelXpert Reliability Simulation User Guide
You may also contact your Cadence support AE for guidance.
For more information on Cadence products and services, visit www.cadence.com.
About Spectre Tech Tips
Spectre Tech Tips is a blog series aimed at exploring the capabilities and potential of Spectre®. In addition to providing insight into the useful features and enhancements in Spectre, this series broadcasts the voice of different bloggers and experts, who share their knowledge and experience on all things related to Spectre. Enter your email address in the Subscriptions box at the top of the page and click SUBSCRIBE NOW to receive notifications about our latest Spectre Tech Tips posts.
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Virtuosity: Identifying Those Traces
With the ever-increasing number of simulations required to be run these days, the sheer number of plots can be overwhelming and it can be difficult to figure out which Cadence Virtuoso ADE XL, Virtuoso ADE Assembler or Virtuoso ADE Explorer history, test or corner each plot belongs to.
To help with this, from IC.6.1.8/ICADVM18.1 Virtuoso Visualization and Analysis we have made identifying and comparing traces across tests and histories much simpler.(read more)![]()
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Virtuosity: Reading Vector Files in Virtuoso Visualization and Analysis
Prior to IC6.1.8 and ICADVM18.1, to view digital and analog waveforms along with the applied stimuli, it was necessary to run the simulations using both digital and analog solvers. This could be a time-consuming process. However, now you can read in the digital stimuli files directly into Cadence Virtuoso Visualization and Analysis, the ADE waveform window. In addition, you can plot the analog waveforms using the stimuli.
The ADE waveform window supports the reading of vector files of the following formats - Value Change Dump (VCD) and Digital Vector File (VEC). Such vector files can be opened through the Results Browser just like other files.
(read more)![]()
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Virtuosity: Saving Time, Effort, and Money with Express Pcells
Use the Express Pcell feature and see for yourself how you can save time, effort, and money!(read more)![]()
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Accurate Pin-to-Pin Resistance Modeling for Wide, Slotted Metal Structures Using Advanced Adaptive Mesh Extraction Technology in Quantus
In Analog/RF layouts, designers frequently use slotted metal structures. Such slotting is done either to satisfy DRC requirements from foundries to satisfy max. density rule criteria, or to reduce eddy current losses in return paths of a transmission line/coiled spiral inductor. Current flow in such slotted metal structures is non-uniform, hence, traditional parasitic extraction approaches with predefined fracture length specifications do not result in accurate pin-to-pin resistance. Hence, Cadence Design Systems sign-off extraction solution – Quantus, provides a mesh extraction approach for these cases, where the slotted/wide metal structures are broken down into smaller squares each representing a small parasitic resistance. This approach of moving from a lumped to distributed model for resistance extraction leads to much better DC V/I current modelling. For example, the MIMCAP layout structure shown below has its 2 terminals ctm (top) and cbm (bot), connected to Metal 13 for its VSS and VDD connections. Its ESR (Effective Series Resistance) is calculated at 50GHz by doing an AC V/I simulation.
Image Source: PVS Quick View Editor
ESR @ 50GHz with regular square counting based extraction is 19.04 ohms (incorrect), whereas by using advanced adaptive mesh gives 5.16 ohms (correct). The MIMCAP structure has very wide top and bottom terminals which needs to be modeled using mesh approach to give accurate results. However, the challenge with this approach is increased netlist size, simulation run time and user overhead in setting up the mesh layers and corresponding mesh sizes to be extracted.
Quantus has newly introduced advanced adaptive mesh extraction, where intelligent meshing is applied to automatically detect non-uniform current regions near discontinuous/slotted metal structures where adaptive grid meshing is applied and detect uniform current regions near continuous metal structures where square counting-based meshing is applied.
The below case study is performed on a ST BiCMOS 55nm process. However, the advanced adaptive mesh technology can be applied to other advanced technology nodes too with similar benefits.
Image Source: Cadence Virtuoso Layout Editor
Adaptive mesh fractured the M1 slotted ground plane by using smaller fracture regions even in right most regions of the layout structure, where there are no slots and current flow is uniform. Whereas, the new Advanced adaptive mesh (available in latest Quantus builds) was able to automatically distinguish between the slotted and continuous metal regions and apply intelligent meshing only near the slotted metal portion, where current flow would be non-uniform and distributed modelling is required. Also, in Advanced adaptive mesh, the size per mesh is 5.96x5.96 which is larger than the 2.59x2.59 determined automatically in Adaptive mesh. Since each fractured square region corresponds to 1 parasitic resistor, this helps reduce the total number of parasitic resistors. A combination of these 2 techniques, helped reduce the netlist size dramatically by ~34%.
In cases where only a certain region of the layout structure needs distributed modelling, meshR user region can be defined, so that Quantus performs advanced adaptive or adaptive meshing in only a certain portion of the layout, whereas the remaining would be square counting based fracturing approach. This further helps reduce netlist size.
The reduction in number of parasitic R and C’s in the advanced adaptive mesh netlist as a result can speed up downstream simulation run time while consuming lesser memory. Its critical to also ascertain the accuracy of the reduced netlist wrt. adaptive mesh to confirm the reduction doesn’t come at the cost of accuracy. Hence, a pin-to-pin DC resistance check is performed on few fractured sub-nodes from the 2 DSPF netlists, keeping in mind the sub-nodes are picked with roughly similar x,y coordinates. Advanced adaptive mesh can also be applied to spice extracted view output formats. As demonstrated, pin to pin resistance accuracy in advanced adaptive mesh is highly accurate.
Depending on the level of simulation accuracy needed, there is a capability to specify a k-scaling factor to increase or decrease the auto mesh size. This helps fine tune the netlist size vs. simulation accuracy desired.
The Adaptive Mesh feature is based on the user-specified mesh size for the conductor layers that are to be meshed. Alternatively, Advanced Adaptive Mesh feature is based on automatic mesh sizing for the conductor layers. Thus, setup and usage of Advanced adaptive mesh is simpler for these users. With the advent of advanced nodes and slotted layout structures, distributed MIMCAPs designs and other newer design artifacts, it is recommended to use the Advanced adaptive mesh solution in Quantus to achieve better netlist size, accuracy and simulation run times.
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Virtuosity: What's New in Run Plan – Part III
After two interesting blogs by Yagya Mishra that explained the most popular features of the Run Plan assistant in Virtuoso ADE Assembler , I am writing this third blog in the series to share with you the latest features introduced in the IC6.1.8 and ICADVM18.1 releases.(read more)![]()
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Spectre Tech Tips: Optimizing Spectre APS Performance
This blog discusses how to optimize the Spectre APS performance for analog and mixed-signal designs. It introduces the key options for adjusting simulation accuracy and performance, provides solutions for typical setup problems causing performance issues, and delivers tips on advanced methods for optimizing simulation performance.(read more)![]()
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Virtuosity: Introducing the Pin Tool
The Pin Tool follows an object-based approach to working with pins by consolidating and redefining the tasks under one umbrella. Various pin-related tasks are grouped in a logical design flow in the various menus in the Pin Tool. The tool includes several new options that let you perform a wide range of pin-related tasks.(read more)![]()
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Virtuosity: Maestro Plotting Templates
Waveforms, plots, graphs, measurements, markers... are all a part and parcel of any circuit designer’s everyday life.
For a regular user of Virtuoso ADE Explorer or Virtuoso ADE Assembler and the ADE waveform window, packaged with IC6.1.6/IC6.1.7 release, it was a common task to redo the measurements on plots every time the plot was refreshed or when a new simulation was set up.
How about a feature that lets you save the snapshot of the markers, zoom levels or any of the plot customizations? In addition, what if you are allowed to reuse this saved snapshot for later simulations? Or, let’s say you want to check a few different measurements on the waveform, for example, a delay, a rise time and a maximum value and use it across different runs.
And here you go... the most eagerly awaited Plotting Templates feature is here in IC6.1.8 and ICADVM18.1(read more)![]()
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Virtuoso IC6.1.8 ISR2 and ICADVM18.1 ISR2 Now Available
The IC6.1.8 ISR2 and ICADVM18.1 ISR2 production releases are now available for download. (read more)![]()
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Virtuosity: What's New in Run Plan – Part III
After two interesting blogs by Yagya Mishra that explained the most popular features of the Run Plan assistant in Virtuoso ADE Assembler , I am writing this third blog in the series to share with you the latest features introduced in the IC6.1.8 and ICADVM18.1 releases.(read more)![]()
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Spectre Tech Tips: Optimizing Spectre APS Performance
This blog discusses how to optimize the Spectre APS performance for analog and mixed-signal designs. It introduces the key options for adjusting simulation accuracy and performance, provides solutions for typical setup problems causing performance issues, and delivers tips on advanced methods for optimizing simulation performance.(read more)![]()
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Virtuosity: Introducing the Pin Tool
The Pin Tool follows an object-based approach to working with pins by consolidating and redefining the tasks under one umbrella. Various pin-related tasks are grouped in a logical design flow in the various menus in the Pin Tool. The tool includes several new options that let you perform a wide range of pin-related tasks.(read more)![]()
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Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction
An important requirement for project sign-off is to ensure that all the design simulations in ADE Assembler are run using the efficient (or pre-defined) sets of operating conditions (corners, sweeps, model files and so) in accordance to the project. ADE Assembler and ADE Verifier now allow you to plan and create project-specific master setups that you can use to create setups for individual tests in ADE Assembler. This enables quick and efficient setup creation at the test level. While Verifying the top-to-down progress of your design using ADE Verifier, you can compare the implementation histories with defined operating conditions from master setup and review the progress of your design based on Analog Coverage percentage reported by ADE Verifier. This blog briefly describes the value of Setup Library Assistant in ADE Assembler and ADE Verifier.(read more)![]()
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Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available
The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download. (read more)![]()
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