This blog describes the EM and IR analyses in Virtuoso ADE as a design sign-off step. It take you to the videos demonstarting the analyses and how to set them up.(read more)![]()
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Virtuoso Video Diary: What Makes EM/IR Analysis A Significant Sign-Off Step?
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Spectre Tech Tips: Spectre Assert and Design Check Overview
As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre APS for analyzing your designs. Besides performing Spectre simulations to verify that the design works as expected, you may want to check your design for critical device conditions, or typical design problems, such as high impedance nodes, leakage paths, or power consumption problems. This blog provides an overview of the Spectre assert, the design check, and the Safe Operation Area (SOA) check functionalities and explains when to use which.(read more)![]()
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Virtuoso Video Diary: Checking EM Compliance Before Creating Layouts
How about checking your designs for electromigration (EM) compliance before creating layouts? Why not? Read further to know more ...(read more)![]()
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Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction
An important requirement for project sign-off is to ensure that all the design simulations in ADE Assembler are run using the efficient (or pre-defined) sets of operating conditions (corners, sweeps, model files and so) in accordance to the project. ADE Assembler and ADE Verifier now allow you to plan and create project-specific master setups that you can use to create setups for individual tests in ADE Assembler. This enables quick and efficient setup creation at the test level. While Verifying the top-to-down progress of your design using ADE Verifier, you can compare the implementation histories with defined operating conditions from master setup and review the progress of your design based on Analog Coverage percentage reported by ADE Verifier. This blog briefly describes the value of Setup Library Assistant in ADE Assembler and ADE Verifier.(read more)![]()
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Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available
The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download. (read more)![]()
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Virtuosity: Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further!
Cutting-edge innovation…Top-down planning…Reliableand formalized verification…Scalable performance!
These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the new release of Virtuoso® ADE Verifier in IC6.1.8 and ICADVM18.1. Analog verification methodology is ever-changing. With the introduction of very large and complex verification project setups involving multiple users, the verification standards and market pressure require much more from the software. Verifier is a comprehensive application that performs plan-based verification of analog and mixed-signal designs. The latest IC release of Verifier brings much anticipated improvements that any verification manager will relish.
The internal architecture for Verifier has been upgraded to take performance, speed, and verification to the next level. The illustration below describes the high-level data structure of the new Verifier flow.
To support these architectural enhancements, we have made the following improvements:
- Performance: Improved performance enables faster verification of larger and more complex designs.
- Simulation Planning and Coverage Environment: Introduction of the Setup Library Assistant (SLA) in ADE Assembler and ADE Verifier enables planning and creation of project-specific master setups. In ADE Assembler, you can quickly and efficiently create setups at the test level using these master setups. In ADE Verifier, you can verify the top-to-down progress of your design by comparing the implementation histories with defined operating conditions from the master setups and reviewing the progress of your design based on the reported Analog Coverage percentage.
- Cellview Updates: On-demand updates, file based-monitoring, and the absence of update loops help in increasing performance.
- Sharing of Data: Direct sharing of data with ADE Assembler is now possible.
- UI Responsiveness: More responsive UI with intuitive forms, menus, and toolbars make the interface more user-friendly than ever.
- External Cellviews: Refashioned external reference flow to support unidirectional references to multiple Verifier cellviews provides a multi-level hierarchy, allowing more flexibility for designers, and the latest verification status to the project manager.
- SKILL Functions: New and improved task-oriented SKILL functions are now available.
- Flows: Improved flows for new assistants and filters, together with flows for exporting and importing CSV, Excel, and mapping files.
Try out the brand-new Verifier in IC6.1.8 and ICADVM18.1 to know how you can do more with your design project verification!
Related Resources
Rapid Adoption Kits
Videos
Blog
User Guides
For more information on Cadence circuit design products and services, visit www.cadence.com.
About Virtuosity
Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more… Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuosity posts.
Happy Reading!
Rashmi Girdhar
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Break the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET Design
How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda of Toshiba Memory (TMC) discloses his recipe today.(read more)![]()
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Virtuosity: In-design Electromigration Analysis - An efficient way to make layouts electrically correct
Shrinking size of ICs with highly complex layouts containing billions of transistors and miles of interconnects....all of this doesn't sound new now. The industry has been pretty fast in adopting advanced node designs and has witnessed various innovations to overcome the challenges faced at this level. One of the challenges is accurate and timely analysis of the effects of electromigration (EM) and IR drop, and faster clearance of physical verification of transistor-level designs. In-design electromigration analysis, a unique feature of Virtuoso Layout Suite, helps you address this challenge. Read more...(read more)![]()
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Virtuoso Video Diary: Tune In to the MPT Video Channel
Tune In to the MPT Video Channel to check out a wide range of features easily accessible through the MPT toolbar.(read more)![]()
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Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available
The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download. (read more)![]()
↧
Virtuosity: Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further!
Cutting-edge innovation…Top-down planning…Reliableand formalized verification…Scalable performance!
These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the new release of Virtuoso® ADE Verifier in IC6.1.8 and ICADVM18.1. Analog verification methodology is ever-changing. With the introduction of very large and complex verification project setups involving multiple users, the verification standards and market pressure require much more from the software. Verifier is a comprehensive application that performs plan-based verification of analog and mixed-signal designs. The latest IC release of Verifier brings much anticipated improvements that any verification manager will relish.
The internal architecture for Verifier has been upgraded to take performance, speed, and verification to the next level. The illustration below describes the high-level data structure of the new Verifier flow.
To support these architectural enhancements, we have made the following improvements:
- Performance: Improved performance enables faster verification of larger and more complex designs.
- Simulation Planning and Coverage Environment: Introduction of the Setup Library Assistant (SLA) in ADE Assembler and ADE Verifier enables planning and creation of project-specific master setups. In ADE Assembler, you can quickly and efficiently create setups at the test level using these master setups. In ADE Verifier, you can verify the top-to-down progress of your design by comparing the implementation histories with defined operating conditions from the master setups and reviewing the progress of your design based on the reported Analog Coverage percentage.
- Cellview Updates: On-demand updates, file based-monitoring, and the absence of update loops help in increasing performance.
- Sharing of Data: Direct sharing of data with ADE Assembler is now possible.
- UI Responsiveness: More responsive UI with intuitive forms, menus, and toolbars make the interface more user-friendly than ever.
- External Cellviews: Refashioned external reference flow to support unidirectional references to multiple Verifier cellviews provides a multi-level hierarchy, allowing more flexibility for designers, and the latest verification status to the project manager.
- SKILL Functions: New and improved task-oriented SKILL functions are now available.
- Flows: Improved flows for new assistants and filters, together with flows for exporting and importing CSV, Excel, and mapping files.
Try out the brand-new Verifier in IC6.1.8 and ICADVM18.1 to know how you can do more with your design project verification!
Related Resources
Rapid Adoption Kits
Videos
Blog
User Guides
For more information on Cadence circuit design products and services, visit www.cadence.com.
About Virtuosity
Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more… Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuosity posts.
Happy Reading!
Rashmi Girdhar
↧
Break the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET Design
How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda of Toshiba Memory (TMC) discloses his recipe today.(read more)![]()
↧
Virtuosity: In-design Electromigration Analysis - An efficient way to make layouts electrically correct
Shrinking size of ICs with highly complex layouts containing billions of transistors and miles of interconnects....all of this doesn't sound new now. The industry has been pretty fast in adopting advanced node designs and has witnessed various innovations to overcome the challenges faced at this level. One of the challenges is accurate and timely analysis of the effects of electromigration (EM) and IR drop, and faster clearance of physical verification of transistor-level designs. In-design electromigration analysis, a unique feature of Virtuoso Layout Suite, helps you address this challenge. Read more...(read more)![]()
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Virtuosity: A Smart Extracted View
The Cadence Quantus Smart View is the next generation of the Extracted View in the Virtuoso environment. The Smart View provides the same functionality as the Extracted View, but it uses a highly efficient and scalable storage mechanism. This means that Smart View can manage larger, more complex designs at advanced nodes with a reduced overall extraction run time and netlist size. In fact, the Smart View not only helps with faster netlist generation in Virtuoso ADE, you can also use it to view the parasitics in the layout within a desired threshold and also their net fragment names. You can also use the Smart View properties to analyze values and connectivity details of extracted parasitic elements.(read more)![]()
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Virtuosity: Spring-Cleaned Virtuoso Doc Closet
Most of us know how a spring-cleaned house can look like. But, do you know how the spring-cleaned Virtuoso documentation closet could look like?(read more)![]()
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Virtuosity: Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further!
Cutting-edge innovation…Top-down planning…Reliableand formalized verification…Scalable performance!
These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the new release of Virtuoso® ADE Verifier in IC6.1.8 and ICADVM18.1. Analog verification methodology is ever-changing. With the introduction of very large and complex verification project setups involving multiple users, the verification standards and market pressure require much more from the software. Verifier is a comprehensive application that performs plan-based verification of analog and mixed-signal designs. The latest IC release of Verifier brings much anticipated improvements that any verification manager will relish.
The internal architecture for Verifier has been upgraded to take performance, speed, and verification to the next level. The illustration below describes the high-level data structure of the new Verifier flow.
To support these architectural enhancements, we have made the following improvements:
- Performance: Improved performance enables faster verification of larger and more complex designs.
- Simulation Planning and Coverage Environment: Introduction of the Setup Library Assistant (SLA) in ADE Assembler and ADE Verifier enables planning and creation of project-specific master setups. In ADE Assembler, you can quickly and efficiently create setups at the test level using these master setups. In ADE Verifier, you can verify the top-to-down progress of your design by comparing the implementation histories with defined operating conditions from the master setups and reviewing the progress of your design based on the reported Analog Coverage percentage.
- Cellview Updates: On-demand updates, file based-monitoring, and the absence of update loops help in increasing performance.
- Sharing of Data: Direct sharing of data with ADE Assembler is now possible.
- UI Responsiveness: More responsive UI with intuitive forms, menus, and toolbars make the interface more user-friendly than ever.
- External Cellviews: Refashioned external reference flow to support unidirectional references to multiple Verifier cellviews provides a multi-level hierarchy, allowing more flexibility for designers, and the latest verification status to the project manager.
- SKILL Functions: New and improved task-oriented SKILL functions are now available.
- Flows: Improved flows for new assistants and filters, together with flows for exporting and importing CSV, Excel, and mapping files.
Try out the brand-new Verifier in IC6.1.8 and ICADVM18.1 to know how you can do more with your design project verification!
Related Resources
Rapid Adoption Kits
Videos
Blog
User Guides
For more information on Cadence circuit design products and services, visit www.cadence.com.
About Virtuosity
Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more… Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuosity posts.
Happy Reading!
Rashmi Girdhar
↧
Break the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET Design
How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda of Toshiba Memory (TMC) discloses his recipe today.(read more)![]()
↧
↧
Virtuosity: In-design Electromigration Analysis - An efficient way to make layouts electrically correct
Shrinking size of ICs with highly complex layouts containing billions of transistors and miles of interconnects....all of this doesn't sound new now. The industry has been pretty fast in adopting advanced node designs and has witnessed various innovations to overcome the challenges faced at this level. One of the challenges is accurate and timely analysis of the effects of electromigration (EM) and IR drop, and faster clearance of physical verification of transistor-level designs. In-design electromigration analysis, a unique feature of Virtuoso Layout Suite, helps you address this challenge. Read more...(read more)![]()
↧
Virtuosity: A Smart Extracted View
The Cadence Quantus Smart View is the next generation of the Extracted View in the Virtuoso environment. The Smart View provides the same functionality as the Extracted View, but it uses a highly efficient and scalable storage mechanism. This means that Smart View can manage larger, more complex designs at advanced nodes with a reduced overall extraction run time and netlist size. In fact, the Smart View not only helps with faster netlist generation in Virtuoso ADE, you can also use it to view the parasitics in the layout within a desired threshold and also their net fragment names. You can also use the Smart View properties to analyze values and connectivity details of extracted parasitic elements.(read more)![]()
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Virtuosity: New Flexible Subwindows
Plots in Cadence Virtuoso Visualization and Analysis can be plotted in a window or subwindow. Subwindows allow you to see plots from different analyses side by side. Until IC6.1.8/ICADVM18.1, the subwindows were not very flexible. Now, we've improved these so that you can choose any grid layout of subwindows up to a 6x8 grid. In addition, you can resize the subwindows easily and move them around. These subwindow configurations are also stored as part of the Maestro Plotting Templates, which will be discussed in detail in an upcoming blog.(read more)![]()
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